imx8mq_evk.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <errno.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <miiphy.h>
  13. #include <netdev.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm-generic/gpio.h>
  16. #include <fsl_esdhc_imx.h>
  17. #include <mmc.h>
  18. #include <asm/arch/imx8mq_pins.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/mach-imx/gpio.h>
  21. #include <asm/mach-imx/mxc_i2c.h>
  22. #include <asm/arch/clock.h>
  23. #include <spl.h>
  24. #include <linux/bitops.h>
  25. #include <power/pmic.h>
  26. #include <power/pfuze100_pmic.h>
  27. #include "../common/pfuze.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  30. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  31. static iomux_v3_cfg_t const wdog_pads[] = {
  32. IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  33. };
  34. static iomux_v3_cfg_t const uart_pads[] = {
  35. IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  36. IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  37. };
  38. int board_early_init_f(void)
  39. {
  40. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  41. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  42. set_wdog_reset(wdog);
  43. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  44. return 0;
  45. }
  46. #ifdef CONFIG_FEC_MXC
  47. static int setup_fec(void)
  48. {
  49. struct iomuxc_gpr_base_regs *gpr =
  50. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  51. /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  52. clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
  53. return set_clk_enet(ENET_125MHZ);
  54. }
  55. int board_phy_config(struct phy_device *phydev)
  56. {
  57. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  58. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  59. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  60. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  61. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  62. if (phydev->drv->config)
  63. phydev->drv->config(phydev);
  64. return 0;
  65. }
  66. #endif
  67. int board_init(void)
  68. {
  69. #ifdef CONFIG_FEC_MXC
  70. setup_fec();
  71. #endif
  72. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
  73. init_usb_clk();
  74. #endif
  75. return 0;
  76. }
  77. int board_mmc_get_env_dev(int devno)
  78. {
  79. return devno;
  80. }
  81. int board_late_init(void)
  82. {
  83. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  84. env_set("board_name", "EVK");
  85. env_set("board_rev", "iMX8MQ");
  86. #endif
  87. return 0;
  88. }