IxNpeMhMacros_p.h 5.7 KB

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  1. /**
  2. * @file IxNpeMhMacros_p.h
  3. *
  4. * @author Intel Corporation
  5. * @date 21 Jan 2002
  6. *
  7. * @brief This file contains the macros for the IxNpeMh component.
  8. *
  9. *
  10. * @par
  11. * IXP400 SW Release version 2.0
  12. *
  13. * -- Copyright Notice --
  14. *
  15. * @par
  16. * Copyright 2001-2005, Intel Corporation.
  17. * All rights reserved.
  18. *
  19. * @par
  20. * SPDX-License-Identifier: BSD-3-Clause
  21. * @par
  22. * -- End of Copyright Notice --
  23. */
  24. /**
  25. * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
  26. *
  27. * @brief Macros for the IxNpeMh component.
  28. *
  29. * @{
  30. */
  31. #ifndef IXNPEMHMACROS_P_H
  32. #define IXNPEMHMACROS_P_H
  33. /* if we are running as a unit test */
  34. #ifdef IX_UNIT_TEST
  35. #undef NDEBUG
  36. #endif /* #ifdef IX_UNIT_TEST */
  37. #include "IxOsal.h"
  38. /*
  39. * #defines for function return types, etc.
  40. */
  41. #define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
  42. #define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
  43. /**
  44. * @def IX_NPEMH_SHOW
  45. *
  46. * @brief Macro for displaying a stat preceded by a textual description.
  47. */
  48. #define IX_NPEMH_SHOW(TEXT, STAT) \
  49. ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
  50. "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
  51. /*
  52. * Prototypes for interface functions.
  53. */
  54. /**
  55. * @typedef IxNpeMhTraceTypes
  56. *
  57. * @brief Enumeration defining IxNpeMh trace levels
  58. */
  59. typedef enum
  60. {
  61. IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */
  62. IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */
  63. IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
  64. IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */
  65. } IxNpeMhTraceTypes;
  66. #ifdef IX_UNIT_TEST
  67. #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
  68. #else
  69. #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
  70. #endif
  71. /**
  72. * @def IX_NPEMH_TRACE0
  73. *
  74. * @brief Trace macro taking 0 arguments.
  75. */
  76. #define IX_NPEMH_TRACE0(LEVEL, STR) \
  77. IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
  78. /**
  79. * @def IX_NPEMH_TRACE1
  80. *
  81. * @brief Trace macro taking 1 argument.
  82. */
  83. #define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
  84. IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
  85. /**
  86. * @def IX_NPEMH_TRACE2
  87. *
  88. * @brief Trace macro taking 2 arguments.
  89. */
  90. #define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
  91. IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
  92. /**
  93. * @def IX_NPEMH_TRACE3
  94. *
  95. * @brief Trace macro taking 3 arguments.
  96. */
  97. #define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
  98. IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
  99. /**
  100. * @def IX_NPEMH_TRACE4
  101. *
  102. * @brief Trace macro taking 4 arguments.
  103. */
  104. #define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
  105. IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
  106. /**
  107. * @def IX_NPEMH_TRACE5
  108. *
  109. * @brief Trace macro taking 5 arguments.
  110. */
  111. #define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
  112. IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
  113. /**
  114. * @def IX_NPEMH_TRACE6
  115. *
  116. * @brief Trace macro taking 6 arguments.
  117. */
  118. #define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
  119. { \
  120. if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
  121. { \
  122. (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
  123. (int)(ARG1), (int)(ARG2), (int)(ARG3), \
  124. (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
  125. } \
  126. }
  127. /**
  128. * @def IX_NPEMH_ERROR_REPORT
  129. *
  130. * @brief Error reporting facility.
  131. */
  132. #define IX_NPEMH_ERROR_REPORT(STR) \
  133. { \
  134. (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
  135. (STR), 0, 0, 0, 0, 0, 0); \
  136. }
  137. /* if we are running on XScale, i.e. real environment */
  138. #if CPU==XSCALE
  139. /**
  140. * @def IX_NPEMH_REGISTER_READ
  141. *
  142. * @brief This macro reads a memory-mapped register.
  143. */
  144. #define IX_NPEMH_REGISTER_READ(registerAddress, value) \
  145. { \
  146. *value = IX_OSAL_READ_LONG(registerAddress); \
  147. }
  148. /**
  149. * @def IX_NPEMH_REGISTER_READ_BITS
  150. *
  151. * @brief This macro partially reads a memory-mapped register.
  152. */
  153. #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
  154. { \
  155. *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
  156. }
  157. /**
  158. * @def IX_NPEMH_REGISTER_WRITE
  159. *
  160. * @brief This macro writes a memory-mapped register.
  161. */
  162. #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
  163. { \
  164. IX_OSAL_WRITE_LONG(registerAddress, value); \
  165. }
  166. /**
  167. * @def IX_NPEMH_REGISTER_WRITE_BITS
  168. *
  169. * @brief This macro partially writes a memory-mapped register.
  170. */
  171. #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
  172. { \
  173. UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
  174. orig &= (~mask); \
  175. orig |= (value & mask); \
  176. IX_OSAL_WRITE_LONG(registerAddress, orig); \
  177. }
  178. /* if we are running as a unit test */
  179. #else /* #if CPU==XSCALE */
  180. #include "IxNpeMhTestRegister.h"
  181. /**
  182. * @def IX_NPEMH_REGISTER_READ
  183. *
  184. * @brief This macro reads a memory-mapped register.
  185. */
  186. #define IX_NPEMH_REGISTER_READ(registerAddress, value) \
  187. { \
  188. ixNpeMhTestRegisterRead (registerAddress, value); \
  189. }
  190. /**
  191. * @def IX_NPEMH_REGISTER_READ_BITS
  192. *
  193. * @brief This macro partially reads a memory-mapped register.
  194. */
  195. #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
  196. { \
  197. ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
  198. }
  199. /**
  200. * @def IX_NPEMH_REGISTER_WRITE
  201. *
  202. * @brief This macro writes a memory-mapped register.
  203. */
  204. #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
  205. { \
  206. ixNpeMhTestRegisterWrite (registerAddress, value); \
  207. }
  208. /**
  209. * @def IX_NPEMH_REGISTER_WRITE_BITS
  210. *
  211. * @brief This macro partially writes a memory-mapped register.
  212. */
  213. #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
  214. { \
  215. ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
  216. }
  217. #endif /* #if CPU==XSCALE */
  218. #endif /* IXNPEMHMACROS_P_H */
  219. /**
  220. * @} defgroup IxNpeMhMacros_p
  221. */