IxNpeA.h 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758
  1. #ifndef __doxygen_HIDE /* This file is not part of the API */
  2. /**
  3. * @file IxNpeA.h
  4. *
  5. * @date 22-Mar-2002
  6. *
  7. * @brief Header file for the IXP400 ATM NPE API
  8. *
  9. *
  10. * @par
  11. * IXP400 SW Release version 2.0
  12. *
  13. * -- Copyright Notice --
  14. *
  15. * @par
  16. * Copyright 2001-2005, Intel Corporation.
  17. * All rights reserved.
  18. *
  19. * @par
  20. * SPDX-License-Identifier: BSD-3-Clause
  21. * @par
  22. * -- End of Copyright Notice --
  23. */
  24. /**
  25. * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
  26. *
  27. * @brief The Public API for the IXP400 NPE-A
  28. *
  29. * @{
  30. */
  31. #ifndef IX_NPE_A_H
  32. #define IX_NPE_A_H
  33. #include "IxQMgr.h"
  34. #include "IxOsal.h"
  35. #include "IxQueueAssignments.h"
  36. /* General Message Ids */
  37. /* ATM Message Ids */
  38. /**
  39. * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
  40. *
  41. * @brief ATM Message ID command to write the data to the offset in the
  42. * Utopia Configuration Table
  43. */
  44. #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE 0x20
  45. /**
  46. * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
  47. *
  48. * @brief ATM Message ID command triggers the NPE to copy the Utopia
  49. * Configuration Table to the Utopia coprocessor
  50. */
  51. #define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD 0x21
  52. /**
  53. * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
  54. *
  55. * @brief ATM Message ID command triggers the NPE to read-back the Utopia
  56. * status registers and update the Utopia Status Table.
  57. */
  58. #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD 0x22
  59. /**
  60. * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
  61. *
  62. * @brief ATM Message ID command to read the Utopia Status Table at the
  63. * specified offset.
  64. */
  65. #define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ 0x23
  66. /**
  67. * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
  68. *
  69. * @brief ATM Message ID command triggers the NPE to re-enable processing
  70. * of any entries on the TxVcQ for this port.
  71. *
  72. * This command will be ignored for a port already enabled
  73. */
  74. #define IX_NPE_A_MSSG_ATM_TX_ENABLE 0x25
  75. /**
  76. * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
  77. *
  78. * @brief ATM Message ID command triggers the NPE to disable processing on
  79. * this port
  80. *
  81. * This command will be ignored for a port already disabled
  82. */
  83. #define IX_NPE_A_MSSG_ATM_TX_DISABLE 0x26
  84. /**
  85. * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
  86. *
  87. * @brief ATM Message ID command triggers the NPE to process any received
  88. * cells for this VC according to the VC Lookup Table.
  89. *
  90. * Re-issuing this command with different contents for a VC that is not
  91. * disabled will cause unpredictable behavior.
  92. */
  93. #define IX_NPE_A_MSSG_ATM_RX_ENABLE 0x27
  94. /**
  95. * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
  96. *
  97. * @brief ATM Message ID command triggers the NPE to disable processing for
  98. * this VC.
  99. *
  100. * This command will be ignored for a VC already disabled
  101. */
  102. #define IX_NPE_A_MSSG_ATM_RX_DISABLE 0x28
  103. /**
  104. * @def IX_NPE_A_MSSG_ATM_STATUS_READ
  105. *
  106. * @brief ATM Message ID command to read the ATM status. The data is returned via
  107. * a response message
  108. */
  109. #define IX_NPE_A_MSSG_ATM_STATUS_READ 0x29
  110. /*--------------------------------------------------------------------------
  111. * HSS Message IDs
  112. *--------------------------------------------------------------------------*/
  113. /**
  114. * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
  115. *
  116. * @brief HSS Message ID command writes the ConfigWord value to the location
  117. * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
  118. */
  119. #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE 0x40
  120. /**
  121. * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
  122. *
  123. * @brief HSS Message ID command triggers the NPE to copy the contents of the
  124. * HSS Configuration Table to the appropriate configuration registers in the
  125. * HSS coprocessor for the port specified by hPort.
  126. */
  127. #define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD 0x41
  128. /**
  129. * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
  130. *
  131. * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
  132. * message for HSS port hPort.
  133. */
  134. #define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ 0x42
  135. /**
  136. * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
  137. *
  138. * @brief HSS Message ID command triggers the NPE to reset internal status and
  139. * enable the HssChannelized operation on the HSS port specified by hPort.
  140. */
  141. #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE 0x43
  142. /**
  143. * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
  144. *
  145. * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
  146. * operation on the HSS port specified by hPort.
  147. */
  148. #define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE 0x44
  149. /**
  150. * @def IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
  151. *
  152. * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
  153. * port hPort. (n=hPort)
  154. */
  155. #define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE 0x45
  156. /**
  157. * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
  158. *
  159. * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
  160. * port hPort. (n=hPort)
  161. */
  162. #define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE 0x46
  163. /**
  164. * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
  165. *
  166. * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
  167. * port hPort. (n=hPort)
  168. */
  169. #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE 0x47
  170. /**
  171. * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
  172. *
  173. * @brief HSS Message ID command writes the HSSnC_RX_BUF_SIZEB and
  174. * HSSnC_RX_TRIG_PERIOD values for HSS port hPort. (n=hPort)
  175. */
  176. #define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE 0x48
  177. /**
  178. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
  179. *
  180. * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
  181. * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW values
  182. * for HSS port hPort. (n=hPort)
  183. */
  184. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE 0x49
  185. /**
  186. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
  187. * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
  188. * port hPort. (n=hPort)
  189. */
  190. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE 0x4A
  191. /**
  192. * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
  193. *
  194. * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
  195. * port hPort. (n=hPort)
  196. */
  197. #define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE 0x4B
  198. /**
  199. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
  200. *
  201. * @brief HSS Message ID command triggers the NPE to reset internal status and
  202. * enable the HssPacketized operation for the flow specified by pPipe on
  203. * the HSS port specified by hPort.
  204. */
  205. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE 0x50
  206. /**
  207. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
  208. * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
  209. * operation for the flow specified by pPipe on the HSS port specified by hPort.
  210. */
  211. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE 0x51
  212. /**
  213. * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
  214. * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
  215. * port hPort.(n=hPort)
  216. */
  217. #define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE 0x52
  218. /**
  219. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
  220. *
  221. * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
  222. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  223. */
  224. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53
  225. /**
  226. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
  227. *
  228. * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
  229. * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
  230. * (n=hPort, p=pPipe)
  231. */
  232. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE 0x54
  233. /**
  234. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
  235. *
  236. * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
  237. * for packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  238. */
  239. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55
  240. /**
  241. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
  242. *
  243. * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
  244. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  245. */
  246. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE 0x56
  247. /**
  248. * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
  249. *
  250. * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
  251. * packet-pipe pPipe on HSS port hPort. (n=hPort, p=pPipe)
  252. */
  253. #define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE 0x57
  254. /* Queue Entry Masks */
  255. /*--------------------------------------------------------------------------
  256. * ATM Descriptor Structure offsets
  257. *--------------------------------------------------------------------------*/
  258. /**
  259. * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
  260. *
  261. * @brief ATM Descriptor structure offset for Receive Descriptor Status field
  262. *
  263. * It is used for descriptor error reporting.
  264. */
  265. #define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET 0
  266. /**
  267. * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
  268. *
  269. * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
  270. *
  271. * It is used to hold an identifier number for this VC
  272. */
  273. #define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET 1
  274. /**
  275. * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
  276. *
  277. * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
  278. * Size field
  279. *
  280. * Number of bytes the current mbuf data buffer can hold
  281. */
  282. #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET 2
  283. /**
  284. * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
  285. *
  286. * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
  287. */
  288. #define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET 4
  289. /**
  290. * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
  291. *
  292. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
  293. *
  294. *
  295. * RX - Initialized to zero. The NPE updates this field as each cell is received and
  296. * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
  297. */
  298. #define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET 12
  299. /**
  300. * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
  301. *
  302. * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
  303. *
  304. * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
  305. */
  306. #define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET 14
  307. /**
  308. * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
  309. *
  310. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
  311. *
  312. * The current mbuf pointer of a chain of mbufs.
  313. */
  314. #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET 20
  315. /**
  316. * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
  317. *
  318. * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
  319. *
  320. * Pointer to the next byte to be read or next free location to be written.
  321. */
  322. #define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET 24
  323. /**
  324. * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET
  325. *
  326. * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer
  327. *
  328. * Pointer to the next MBuf in a chain of MBufs.
  329. */
  330. #define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET 28
  331. /**
  332. * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET
  333. *
  334. * @brief ATM Descriptor structure offset for Receive Descriptor Total Length
  335. *
  336. * Total number of bytes written to the chain of MBufs by the NPE
  337. */
  338. #define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET 32
  339. /**
  340. * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
  341. *
  342. * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue
  343. *
  344. * Current CRC value for a PDU
  345. */
  346. #define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36
  347. /**
  348. * @def IX_NPE_A_RXDESCRIPTOR_SIZE
  349. *
  350. * @brief ATM Descriptor structure offset for Receive Descriptor Size
  351. *
  352. * The size of the Receive descriptor
  353. */
  354. #define IX_NPE_A_RXDESCRIPTOR_SIZE 40
  355. /**
  356. * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET
  357. *
  358. * @brief ATM Descriptor structure offset for Transmit Descriptor Port
  359. *
  360. * Port identifier.
  361. */
  362. #define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET 0
  363. /**
  364. * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET
  365. *
  366. * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD
  367. */
  368. #define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET 1
  369. /**
  370. * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET
  371. *
  372. * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length
  373. *
  374. * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer.
  375. * The NPE decrements this field for every transmitted cell. Thus, when the NPE writes a
  376. * descriptor the TxDone queue, this field will equal zero.
  377. */
  378. #define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET 2
  379. /**
  380. * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET
  381. * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header
  382. */
  383. #define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET 4
  384. /**
  385. * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET
  386. *
  387. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain
  388. */
  389. #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET 8
  390. /**
  391. * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET
  392. *
  393. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data
  394. *
  395. * Pointer to the next byte to be read or next free location to be written.
  396. */
  397. #define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET 12
  398. /**
  399. * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET
  400. *
  401. * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain
  402. */
  403. #define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET 16
  404. /**
  405. * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET
  406. *
  407. * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length
  408. *
  409. * Total number of bytes written to the chain of MBufs by the NPE
  410. */
  411. #define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET 20
  412. /**
  413. * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET
  414. *
  415. * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue
  416. *
  417. * Current CRC value for a PDU
  418. */
  419. #define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24
  420. /**
  421. * @def IX_NPE_A_TXDESCRIPTOR_SIZE
  422. *
  423. * @brief ATM Descriptor structure offset for Transmit Descriptor Size
  424. */
  425. #define IX_NPE_A_TXDESCRIPTOR_SIZE 28
  426. /**
  427. * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX
  428. *
  429. * @brief Maximum number of chained MBufs that can be chained together
  430. */
  431. #define IX_NPE_A_CHAIN_DESC_COUNT_MAX 256
  432. /*
  433. * Definition of the ATM cell header
  434. *
  435. * This would most conviently be defined as the bit field shown below.
  436. * Endian portability prevents this, therefore a set of macros
  437. * are defined to access the fields within the cell header assumed to
  438. * be passed as a UINT32.
  439. *
  440. * Changes to field sizes or orders must be reflected in the offset
  441. * definitions above.
  442. *
  443. * typedef struct
  444. * {
  445. * unsigned int gfc:4;
  446. * unsigned int vpi:8;
  447. * unsigned int vci:16;
  448. * unsigned int pti:3;
  449. * unsigned int clp:1;
  450. * } IxNpeA_AtmCellHeader;
  451. *
  452. */
  453. /** Mask to acess GFC */
  454. #define GFC_MASK 0xf0000000
  455. /** return GFC from ATM cell header */
  456. #define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \
  457. (((header) & GFC_MASK) >> 28)
  458. /** set GFC into ATM cell header */
  459. #define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \
  460. do { \
  461. (header) &= ~GFC_MASK; \
  462. (header) |= (((gfc) << 28) & GFC_MASK); \
  463. } while(0)
  464. /** Mask to acess VPI */
  465. #define VPI_MASK 0x0ff00000
  466. /** return VPI from ATM cell header */
  467. #define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \
  468. (((header) & VPI_MASK) >> 20)
  469. /** set VPI into ATM cell header */
  470. #define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \
  471. do { \
  472. (header) &= ~VPI_MASK; \
  473. (header) |= (((vpi) << 20) & VPI_MASK); \
  474. } while(0)
  475. /** Mask to acess VCI */
  476. #define VCI_MASK 0x000ffff0
  477. /** return VCI from ATM cell header */
  478. #define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \
  479. (((header) & VCI_MASK) >> 4)
  480. /** set VCI into ATM cell header */
  481. #define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \
  482. do { \
  483. (header) &= ~VCI_MASK; \
  484. (header) |= (((vci) << 4) & VCI_MASK); \
  485. } while(0)
  486. /** Mask to acess PTI */
  487. #define PTI_MASK 0x0000000e
  488. /** return PTI from ATM cell header */
  489. #define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \
  490. (((header) & PTI_MASK) >> 1)
  491. /** set PTI into ATM cell header */
  492. #define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \
  493. do { \
  494. (header) &= ~PTI_MASK; \
  495. (header) |= (((pti) << 1) & PTI_MASK); \
  496. } while(0)
  497. /** Mask to acess CLP */
  498. #define CLP_MASK 0x00000001
  499. /** return CLP from ATM cell header */
  500. #define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \
  501. ((header) & CLP_MASK)
  502. /** set CLP into ATM cell header */
  503. #define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \
  504. do { \
  505. (header) &= ~CLP_MASK; \
  506. (header) |= ((clp) & CLP_MASK); \
  507. } while(0)
  508. /*
  509. * Definition of the Rx bitfield
  510. *
  511. * This would most conviently be defined as the bit field shown below.
  512. * Endian portability prevents this, therefore a set of macros
  513. * are defined to access the fields within the rxBitfield assumed to
  514. * be passed as a UINT32.
  515. *
  516. * Changes to field sizes or orders must be reflected in the offset
  517. * definitions above.
  518. *
  519. * Rx bitfield
  520. * struct
  521. * { IX_NPEA_RXBITFIELD(
  522. * unsigned int status:1,
  523. * unsigned int port:7,
  524. * unsigned int vcId:8,
  525. * unsigned int currMbufSize:16);
  526. * } rxBitField;
  527. *
  528. */
  529. /** Mask to acess the rxBitField status */
  530. #define STATUS_MASK 0x80000000
  531. /** return the rxBitField status */
  532. #define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \
  533. (((rxbitfield) & STATUS_MASK) >> 31)
  534. /** set the rxBitField status */
  535. #define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \
  536. do { \
  537. (rxbitfield) &= ~STATUS_MASK; \
  538. (rxbitfield) |= (((status) << 31) & STATUS_MASK); \
  539. } while(0)
  540. /** Mask to acess the rxBitField port */
  541. #define PORT_MASK 0x7f000000
  542. /** return the rxBitField port */
  543. #define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \
  544. (((rxbitfield) & PORT_MASK) >> 24)
  545. /** set the rxBitField port */
  546. #define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \
  547. do { \
  548. (rxbitfield) &= ~PORT_MASK; \
  549. (rxbitfield) |= (((port) << 24) & PORT_MASK); \
  550. } while(0)
  551. /** Mask to acess the rxBitField vcId */
  552. #define VCID_MASK 0x00ff0000
  553. /** return the rxBitField vcId */
  554. #define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \
  555. (((rxbitfield) & VCID_MASK) >> 16)
  556. /** set the rxBitField vcId */
  557. #define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \
  558. do { \
  559. (rxbitfield) &= ~VCID_MASK; \
  560. (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \
  561. } while(0)
  562. /** Mask to acess the rxBitField mbuf size */
  563. #define CURRMBUFSIZE_MASK 0x0000ffff
  564. /** return the rxBitField mbuf size */
  565. #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \
  566. ((rxbitfield) & CURRMBUFSIZE_MASK)
  567. /** set the rxBitField mbuf size */
  568. #define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \
  569. do { \
  570. (rxbitfield) &= ~CURRMBUFSIZE_MASK; \
  571. (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \
  572. } while(0)
  573. /**
  574. * @brief Tx Descriptor definition
  575. */
  576. typedef struct
  577. {
  578. UINT8 port; /**< Tx Port number */
  579. UINT8 aalType; /**< AAL Type */
  580. UINT16 currMbufLen; /**< mbuf length */
  581. UINT32 atmCellHeader; /**< ATM cell header */
  582. IX_OSAL_MBUF *pCurrMbuf; /**< pointer to mbuf */
  583. unsigned char *pCurrMbufData; /**< Pointer to mbuf->dat */
  584. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  585. UINT32 totalLen; /**< Total Length */
  586. UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
  587. } IxNpeA_TxAtmVc;
  588. /* Changes to field sizes or orders must be reflected in the offset
  589. * definitions above. */
  590. /**
  591. * @brief Rx Descriptor definition
  592. */
  593. typedef struct
  594. {
  595. UINT32 rxBitField; /**< Received bit field */
  596. UINT32 atmCellHeader; /**< ATM Cell Header */
  597. UINT32 rsvdWord0; /**< Reserved field */
  598. UINT16 currMbufLen; /**< Mbuf Length */
  599. UINT8 timeLimit; /**< Payload Reassembly timeLimit (used for aal0_xx only) */
  600. UINT8 rsvdByte0; /**< Reserved field */
  601. UINT32 rsvdWord1; /**< Reserved field */
  602. IX_OSAL_MBUF *pCurrMbuf; /**< Pointer to current mbuf */
  603. unsigned char *pCurrMbufData; /**< Pointer to current mbuf->data */
  604. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  605. UINT32 totalLen; /**< Total Length */
  606. UINT32 aal5CrcResidue; /**< AAL5 CRC Residue */
  607. } IxNpeA_RxAtmVc;
  608. /**
  609. * @brief NPE-A AAL Type
  610. */
  611. typedef enum
  612. {
  613. IX_NPE_A_AAL_TYPE_INVALID = 0, /**< Invalid AAL type */
  614. IX_NPE_A_AAL_TYPE_0_48 = 0x1, /**< AAL0 - 48 byte */
  615. IX_NPE_A_AAL_TYPE_0_52 = 0x2, /**< AAL0 - 52 byte */
  616. IX_NPE_A_AAL_TYPE_5 = 0x5, /**< AAL5 */
  617. IX_NPE_A_AAL_TYPE_OAM = 0xF /**< OAM */
  618. } IxNpeA_AalType;
  619. /**
  620. * @brief NPE-A Payload format 52-bytes & 48-bytes
  621. */
  622. typedef enum
  623. {
  624. IX_NPE_A_52_BYTE_PAYLOAD = 0, /**< 52 byte payload */
  625. IX_NPE_A_48_BYTE_PAYLOAD /**< 48 byte payload */
  626. } IxNpeA_PayloadFormat;
  627. /**
  628. * @brief HSS Packetized NpePacket Descriptor Structure
  629. */
  630. typedef struct
  631. {
  632. UINT8 status; /**< Status of the packet passed to the client */
  633. UINT8 errorCount; /**< Number of errors */
  634. UINT8 chainCount; /**< Mbuf chain count e.g. 0 - No mbuf chain */
  635. UINT8 rsvdByte0; /**< Reserved byte to make the descriptor word align */
  636. UINT16 packetLength; /**< Packet Length */
  637. UINT16 rsvdShort0; /**< Reserved short to make the descriptor a word align */
  638. IX_OSAL_MBUF *pRootMbuf; /**< Pointer to Root mbuf */
  639. IX_OSAL_MBUF *pNextMbuf; /**< Pointer to next mbuf */
  640. UINT8 *pMbufData; /**< Pointer to the current mbuf->data */
  641. UINT32 mbufLength; /**< Current mbuf length */
  642. } IxNpeA_NpePacketDescriptor;
  643. #endif
  644. /**
  645. *@}
  646. */
  647. #endif /* __doxygen_HIDE */