IxNpeDlNpeMgr.c 26 KB

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  1. /**
  2. * @file IxNpeDlNpeMgr.c
  3. *
  4. * @author Intel Corporation
  5. * @date 09 January 2002
  6. *
  7. * @brief This file contains the implementation of the private API for the
  8. * IXP425 NPE Downloader NpeMgr module
  9. *
  10. *
  11. * @par
  12. * IXP400 SW Release version 2.0
  13. *
  14. * -- Copyright Notice --
  15. *
  16. * @par
  17. * Copyright 2001-2005, Intel Corporation.
  18. * All rights reserved.
  19. *
  20. * @par
  21. * SPDX-License-Identifier: BSD-3-Clause
  22. * @par
  23. * -- End of Copyright Notice --
  24. */
  25. /*
  26. * Put the user defined include files required.
  27. */
  28. #include "IxOsal.h"
  29. #include "IxNpeDl.h"
  30. #include "IxNpeDlNpeMgr_p.h"
  31. #include "IxNpeDlNpeMgrUtils_p.h"
  32. #include "IxNpeDlNpeMgrEcRegisters_p.h"
  33. #include "IxNpeDlMacros_p.h"
  34. #include "IxFeatureCtrl.h"
  35. /*
  36. * #defines and macros used in this file.
  37. */
  38. #define IX_NPEDL_BYTES_PER_WORD 4
  39. /* used to read download map from version in microcode image */
  40. #define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000
  41. #define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001
  42. #define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002
  43. #define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F
  44. /*
  45. * masks used to extract address info from State information context
  46. * register addresses as read from microcode image
  47. */
  48. #define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
  49. #define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
  50. /* LSB offset of Context Number field in State-Info Context Address */
  51. #define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4
  52. /* size (in words) of single State Information entry (ctxt reg address|data) */
  53. #define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
  54. #define IX_NPEDL_RESET_NPE_PARITY 0x0800
  55. #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF
  56. #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF
  57. /*
  58. * Typedefs whose scope is limited to this file.
  59. */
  60. typedef struct
  61. {
  62. UINT32 type;
  63. UINT32 offset;
  64. } IxNpeDlNpeMgrDownloadMapBlockEntry;
  65. typedef union
  66. {
  67. IxNpeDlNpeMgrDownloadMapBlockEntry block;
  68. UINT32 eodmMarker;
  69. } IxNpeDlNpeMgrDownloadMapEntry;
  70. typedef struct
  71. {
  72. /* 1st entry in the download map (there may be more than one) */
  73. IxNpeDlNpeMgrDownloadMapEntry entry[1];
  74. } IxNpeDlNpeMgrDownloadMap;
  75. /* used to access an instruction or data block in a microcode image */
  76. typedef struct
  77. {
  78. UINT32 npeMemAddress;
  79. UINT32 size;
  80. UINT32 data[1];
  81. } IxNpeDlNpeMgrCodeBlock;
  82. /* used to access each Context Reg entry state-information block */
  83. typedef struct
  84. {
  85. UINT32 addressInfo;
  86. UINT32 value;
  87. } IxNpeDlNpeMgrStateInfoCtxtRegEntry;
  88. /* used to access a state-information block in a microcode image */
  89. typedef struct
  90. {
  91. UINT32 size;
  92. IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
  93. } IxNpeDlNpeMgrStateInfoBlock;
  94. /* used to store some useful NPE information for easy access */
  95. typedef struct
  96. {
  97. UINT32 baseAddress;
  98. UINT32 insMemSize;
  99. UINT32 dataMemSize;
  100. } IxNpeDlNpeInfo;
  101. /* used to distinguish instruction and data memory operations */
  102. typedef enum
  103. {
  104. IX_NPEDL_MEM_TYPE_INSTRUCTION = 0,
  105. IX_NPEDL_MEM_TYPE_DATA
  106. } IxNpeDlNpeMemType;
  107. /* used to hold a reset value for a particular ECS register */
  108. typedef struct
  109. {
  110. UINT32 regAddr;
  111. UINT32 regResetVal;
  112. } IxNpeDlEcsRegResetValue;
  113. /* prototype of function to write either Instruction or Data memory */
  114. typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress,
  115. UINT32 npeMemAddress,
  116. UINT32 npeMemData,
  117. BOOL verify);
  118. /* module statistics counters */
  119. typedef struct
  120. {
  121. UINT32 instructionBlocksLoaded;
  122. UINT32 dataBlocksLoaded;
  123. UINT32 stateInfoBlocksLoaded;
  124. UINT32 criticalNpeErrors;
  125. UINT32 criticalMicrocodeErrors;
  126. UINT32 npeStarts;
  127. UINT32 npeStops;
  128. UINT32 npeResets;
  129. } IxNpeDlNpeMgrStats;
  130. /*
  131. * Variable declarations global to this file only. Externs are followed by
  132. * static variables.
  133. */
  134. static IxNpeDlNpeInfo ixNpeDlNpeInfo[] =
  135. {
  136. {
  137. 0,
  138. IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
  139. IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
  140. },
  141. {
  142. 0,
  143. IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
  144. IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
  145. },
  146. {
  147. 0,
  148. IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
  149. IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
  150. }
  151. };
  152. /* contains Reset values for Context Store Registers */
  153. static UINT32 ixNpeDlCtxtRegResetValues[] =
  154. {
  155. IX_NPEDL_CTXT_REG_RESET_STEVT,
  156. IX_NPEDL_CTXT_REG_RESET_STARTPC,
  157. IX_NPEDL_CTXT_REG_RESET_REGMAP,
  158. IX_NPEDL_CTXT_REG_RESET_CINDEX,
  159. };
  160. /* contains Reset values for Context Store Registers */
  161. static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] =
  162. {
  163. {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET},
  164. {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET},
  165. {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET},
  166. {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET},
  167. {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET},
  168. {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET},
  169. {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET},
  170. {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET},
  171. {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET},
  172. {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET},
  173. {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET},
  174. {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET},
  175. {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET}
  176. };
  177. static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats;
  178. /* Set when NPE register memory has been mapped */
  179. static BOOL ixNpeDlMemInitialised = false;
  180. /*
  181. * static function prototypes.
  182. */
  183. PRIVATE IX_STATUS
  184. ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress,
  185. IxNpeDlNpeMgrCodeBlock *codeBlockPtr,
  186. BOOL verify, IxNpeDlNpeMemType npeMemType);
  187. PRIVATE IX_STATUS
  188. ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress,
  189. IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr,
  190. BOOL verify);
  191. PRIVATE BOOL
  192. ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset,
  193. UINT32 expectedBitsSet);
  194. PRIVATE UINT32
  195. ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId);
  196. /*
  197. * Function definition: ixNpeDlNpeMgrBaseAddressGet
  198. */
  199. PRIVATE UINT32
  200. ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId)
  201. {
  202. IX_OSAL_ASSERT (ixNpeDlMemInitialised);
  203. return ixNpeDlNpeInfo[npeId].baseAddress;
  204. }
  205. /*
  206. * Function definition: ixNpeDlNpeMgrInit
  207. */
  208. void
  209. ixNpeDlNpeMgrInit (void)
  210. {
  211. /* Only map the memory once */
  212. if (!ixNpeDlMemInitialised)
  213. {
  214. UINT32 virtAddr;
  215. /* map the register memory for NPE-A */
  216. virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA,
  217. IX_OSAL_IXP400_NPEA_MAP_SIZE);
  218. IX_OSAL_ASSERT(virtAddr);
  219. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr;
  220. /* map the register memory for NPE-B */
  221. virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB,
  222. IX_OSAL_IXP400_NPEB_MAP_SIZE);
  223. IX_OSAL_ASSERT(virtAddr);
  224. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr;
  225. /* map the register memory for NPE-C */
  226. virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC,
  227. IX_OSAL_IXP400_NPEC_MAP_SIZE);
  228. IX_OSAL_ASSERT(virtAddr);
  229. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr;
  230. ixNpeDlMemInitialised = true;
  231. }
  232. }
  233. /*
  234. * Function definition: ixNpeDlNpeMgrUninit
  235. */
  236. IX_STATUS
  237. ixNpeDlNpeMgrUninit (void)
  238. {
  239. if (!ixNpeDlMemInitialised)
  240. {
  241. return IX_FAIL;
  242. }
  243. IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress);
  244. IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress);
  245. IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress);
  246. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0;
  247. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0;
  248. ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0;
  249. ixNpeDlMemInitialised = false;
  250. return IX_SUCCESS;
  251. }
  252. /*
  253. * Function definition: ixNpeDlNpeMgrImageLoad
  254. */
  255. IX_STATUS
  256. ixNpeDlNpeMgrImageLoad (
  257. IxNpeDlNpeId npeId,
  258. UINT32 *imageCodePtr,
  259. BOOL verify)
  260. {
  261. UINT32 npeBaseAddress;
  262. IxNpeDlNpeMgrDownloadMap *downloadMap;
  263. UINT32 *blockPtr;
  264. UINT32 mapIndex = 0;
  265. IX_STATUS status = IX_SUCCESS;
  266. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  267. "Entering ixNpeDlNpeMgrImageLoad\n");
  268. /* get base memory address of NPE from npeId */
  269. npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
  270. /* check execution status of NPE to verify NPE Stop was successful */
  271. if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
  272. IX_NPEDL_EXCTL_STATUS_STOP))
  273. {
  274. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - "
  275. "NPE was not stopped before download\n");
  276. status = IX_FAIL;
  277. }
  278. else
  279. {
  280. /*
  281. * Read Download Map, checking each block type and calling
  282. * appropriate function to perform download
  283. */
  284. downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
  285. while ((downloadMap->entry[mapIndex].eodmMarker !=
  286. IX_NPEDL_END_OF_DOWNLOAD_MAP)
  287. && (status == IX_SUCCESS))
  288. {
  289. /* calculate pointer to block to be downloaded */
  290. blockPtr = imageCodePtr +
  291. downloadMap->entry[mapIndex].block.offset;
  292. switch (downloadMap->entry[mapIndex].block.type)
  293. {
  294. case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
  295. status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
  296. (IxNpeDlNpeMgrCodeBlock *)blockPtr,
  297. verify,
  298. IX_NPEDL_MEM_TYPE_INSTRUCTION);
  299. break;
  300. case IX_NPEDL_BLOCK_TYPE_DATA:
  301. status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress,
  302. (IxNpeDlNpeMgrCodeBlock *)blockPtr,
  303. verify, IX_NPEDL_MEM_TYPE_DATA);
  304. break;
  305. case IX_NPEDL_BLOCK_TYPE_STATE:
  306. status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress,
  307. (IxNpeDlNpeMgrStateInfoBlock *) blockPtr,
  308. verify);
  309. break;
  310. default:
  311. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: "
  312. "unknown block type in download map\n");
  313. status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
  314. ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
  315. break;
  316. }
  317. mapIndex++;
  318. }/* loop: for each entry in download map, while status == SUCCESS */
  319. }/* condition: NPE stopped before attempting download */
  320. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  321. "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n",
  322. status);
  323. return status;
  324. }
  325. /*
  326. * Function definition: ixNpeDlNpeMgrMemLoad
  327. */
  328. PRIVATE IX_STATUS
  329. ixNpeDlNpeMgrMemLoad (
  330. IxNpeDlNpeId npeId,
  331. UINT32 npeBaseAddress,
  332. IxNpeDlNpeMgrCodeBlock *blockPtr,
  333. BOOL verify,
  334. IxNpeDlNpeMemType npeMemType)
  335. {
  336. UINT32 npeMemAddress;
  337. UINT32 blockSize;
  338. UINT32 memSize = 0;
  339. IxNpeDlNpeMgrMemWrite memWriteFunc = NULL;
  340. UINT32 localIndex = 0;
  341. IX_STATUS status = IX_SUCCESS;
  342. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  343. "Entering ixNpeDlNpeMgrMemLoad\n");
  344. /*
  345. * select NPE EXCTL reg read/write commands depending on memory
  346. * type (instruction/data) to be accessed
  347. */
  348. if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
  349. {
  350. memSize = ixNpeDlNpeInfo[npeId].insMemSize;
  351. memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite;
  352. }
  353. else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
  354. {
  355. memSize = ixNpeDlNpeInfo[npeId].dataMemSize;
  356. memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite;
  357. }
  358. /*
  359. * NPE memory is loaded contiguously from each block, so only address
  360. * of 1st word in block is needed
  361. */
  362. npeMemAddress = blockPtr->npeMemAddress;
  363. /* number of words of instruction/data microcode in block to download */
  364. blockSize = blockPtr->size;
  365. if ((npeMemAddress + blockSize) > memSize)
  366. {
  367. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
  368. "Block size too big for NPE memory\n");
  369. status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
  370. ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
  371. }
  372. else
  373. {
  374. for (localIndex = 0; localIndex < blockSize; localIndex++)
  375. {
  376. status = memWriteFunc (npeBaseAddress, npeMemAddress,
  377. blockPtr->data[localIndex], verify);
  378. if (status != IX_SUCCESS)
  379. {
  380. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: "
  381. "write to NPE memory failed\n");
  382. status = IX_NPEDL_CRITICAL_NPE_ERR;
  383. ixNpeDlNpeMgrStats.criticalNpeErrors++;
  384. break; /* abort download */
  385. }
  386. /* increment target (word)address in NPE memory */
  387. npeMemAddress++;
  388. }
  389. }/* condition: block size will fit in NPE memory */
  390. if (status == IX_SUCCESS)
  391. {
  392. if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION)
  393. {
  394. ixNpeDlNpeMgrStats.instructionBlocksLoaded++;
  395. }
  396. else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA)
  397. {
  398. ixNpeDlNpeMgrStats.dataBlocksLoaded++;
  399. }
  400. }
  401. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  402. "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status);
  403. return status;
  404. }
  405. /*
  406. * Function definition: ixNpeDlNpeMgrStateInfoLoad
  407. */
  408. PRIVATE IX_STATUS
  409. ixNpeDlNpeMgrStateInfoLoad (
  410. UINT32 npeBaseAddress,
  411. IxNpeDlNpeMgrStateInfoBlock *blockPtr,
  412. BOOL verify)
  413. {
  414. UINT32 blockSize;
  415. UINT32 ctxtRegAddrInfo;
  416. UINT32 ctxtRegVal;
  417. IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
  418. UINT32 ctxtNum; /* identifies Context number (0-16) */
  419. UINT32 i;
  420. IX_STATUS status = IX_SUCCESS;
  421. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  422. "Entering ixNpeDlNpeMgrStateInfoLoad\n");
  423. /* block size contains number of words of state-info in block */
  424. blockSize = blockPtr->size;
  425. ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
  426. /* for each state-info context register entry in block */
  427. for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++)
  428. {
  429. /* each state-info entry is 2 words (address, value) in length */
  430. ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo;
  431. ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value;
  432. ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
  433. ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
  434. IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
  435. /* error-check Context Register No. and Context Number values */
  436. /* NOTE that there is no STEVT register for Context 0 */
  437. if ((ctxtReg < 0) ||
  438. (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) ||
  439. (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) ||
  440. ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
  441. {
  442. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
  443. "invalid Context Register Address\n");
  444. status = IX_NPEDL_CRITICAL_MICROCODE_ERR;
  445. ixNpeDlNpeMgrStats.criticalMicrocodeErrors++;
  446. break; /* abort download */
  447. }
  448. status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg,
  449. ctxtRegVal, verify);
  450. if (status != IX_SUCCESS)
  451. {
  452. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: "
  453. "write of state-info to NPE failed\n");
  454. status = IX_NPEDL_CRITICAL_NPE_ERR;
  455. ixNpeDlNpeMgrStats.criticalNpeErrors++;
  456. break; /* abort download */
  457. }
  458. }/* loop: for each context reg entry in State Info block */
  459. ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
  460. if (status == IX_SUCCESS)
  461. {
  462. ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++;
  463. }
  464. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  465. "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n",
  466. status);
  467. return status;
  468. }
  469. /*
  470. * Function definition: ixNpeDlNpeMgrNpeReset
  471. */
  472. IX_STATUS
  473. ixNpeDlNpeMgrNpeReset (
  474. IxNpeDlNpeId npeId)
  475. {
  476. UINT32 npeBaseAddress;
  477. IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */
  478. UINT32 ctxtNum; /* identifies Context number (0-16) */
  479. UINT32 regAddr;
  480. UINT32 regVal;
  481. UINT32 localIndex;
  482. UINT32 indexMax;
  483. IX_STATUS status = IX_SUCCESS;
  484. IxFeatureCtrlReg unitFuseReg;
  485. UINT32 ixNpeConfigCtrlRegVal;
  486. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  487. "Entering ixNpeDlNpeMgrNpeReset\n");
  488. /* get base memory address of NPE from npeId */
  489. npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
  490. /* pre-store the NPE Config Control Register Value */
  491. IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal);
  492. ixNpeConfigCtrlRegVal |= 0x3F000000;
  493. /* disable the parity interrupt */
  494. IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
  495. ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress);
  496. /*
  497. * clear the FIFOs
  498. */
  499. while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
  500. IX_NPEDL_REG_OFFSET_WFIFO,
  501. IX_NPEDL_MASK_WFIFO_VALID))
  502. {
  503. /* read from the Watch-point FIFO until empty */
  504. IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO,
  505. &regVal);
  506. }
  507. while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
  508. IX_NPEDL_REG_OFFSET_STAT,
  509. IX_NPEDL_MASK_STAT_OFNE))
  510. {
  511. /* read from the outFIFO until empty */
  512. IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO,
  513. &regVal);
  514. }
  515. while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
  516. IX_NPEDL_REG_OFFSET_STAT,
  517. IX_NPEDL_MASK_STAT_IFNE))
  518. {
  519. /*
  520. * step execution of the NPE intruction to read inFIFO using
  521. * the Debug Executing Context stack
  522. */
  523. status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
  524. IX_NPEDL_INSTR_RD_FIFO, 0, 0);
  525. if (IX_SUCCESS != status)
  526. {
  527. return status;
  528. }
  529. }
  530. /*
  531. * Reset the mailbox reg
  532. */
  533. /* ...from XScale side */
  534. IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST,
  535. IX_NPEDL_REG_RESET_MBST);
  536. /* ...from NPE side */
  537. status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress,
  538. IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
  539. if (IX_SUCCESS != status)
  540. {
  541. return status;
  542. }
  543. /*
  544. * Reset the physical registers in the NPE register file:
  545. * Note: no need to save/restore REGMAP for Context 0 here
  546. * since all Context Store regs are reset in subsequent code
  547. */
  548. for (regAddr = 0;
  549. (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL);
  550. regAddr++)
  551. {
  552. /* for each physical register in the NPE reg file, write 0 : */
  553. status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr,
  554. 0, true);
  555. if (status != IX_SUCCESS)
  556. {
  557. return status; /* abort reset */
  558. }
  559. }
  560. /*
  561. * Reset the context store:
  562. */
  563. for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN;
  564. ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++)
  565. {
  566. /* set each context's Context Store registers to reset values: */
  567. for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++)
  568. {
  569. /* NOTE that there is no STEVT register for Context 0 */
  570. if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT)))
  571. {
  572. regVal = ixNpeDlCtxtRegResetValues[ctxtReg];
  573. status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum,
  574. ctxtReg, regVal, true);
  575. if (status != IX_SUCCESS)
  576. {
  577. return status; /* abort reset */
  578. }
  579. }
  580. }
  581. }
  582. ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress);
  583. /* write Reset values to Execution Context Stack registers */
  584. indexMax = sizeof (ixNpeDlEcsRegResetValues) /
  585. sizeof (IxNpeDlEcsRegResetValue);
  586. for (localIndex = 0; localIndex < indexMax; localIndex++)
  587. {
  588. regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr;
  589. regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal;
  590. ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal);
  591. }
  592. /* clear the profile counter */
  593. ixNpeDlNpeMgrCommandIssue (npeBaseAddress,
  594. IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
  595. /* clear registers EXCT, AP0, AP1, AP2 and AP3 */
  596. for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
  597. regAddr <= IX_NPEDL_REG_OFFSET_AP3;
  598. regAddr += IX_NPEDL_BYTES_PER_WORD)
  599. {
  600. IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0);
  601. }
  602. /* Reset the Watch-count register */
  603. IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0);
  604. /*
  605. * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation
  606. */
  607. /*
  608. * Call the feature control API to fused out and reset the NPE and its
  609. * coprocessor - to reset internal states and remove parity error
  610. */
  611. unitFuseReg = ixFeatureCtrlRead ();
  612. unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId);
  613. ixFeatureCtrlWrite (unitFuseReg);
  614. /* call the feature control API to un-fused and un-reset the NPE & COP */
  615. unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId));
  616. ixFeatureCtrlWrite (unitFuseReg);
  617. /*
  618. * Call NpeMgr function to stop the NPE again after the Feature Control
  619. * has unfused and Un-Reset the NPE and its associated Coprocessors
  620. */
  621. status = ixNpeDlNpeMgrNpeStop (npeId);
  622. /* restore NPE configuration bus Control Register - Parity Settings */
  623. IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL,
  624. (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
  625. ixNpeDlNpeMgrStats.npeResets++;
  626. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  627. "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status);
  628. return status;
  629. }
  630. /*
  631. * Function definition: ixNpeDlNpeMgrNpeStart
  632. */
  633. IX_STATUS
  634. ixNpeDlNpeMgrNpeStart (
  635. IxNpeDlNpeId npeId)
  636. {
  637. UINT32 npeBaseAddress;
  638. UINT32 ecsRegVal;
  639. BOOL npeRunning;
  640. IX_STATUS status = IX_SUCCESS;
  641. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  642. "Entering ixNpeDlNpeMgrNpeStart\n");
  643. /* get base memory address of NPE from npeId */
  644. npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
  645. /*
  646. * ensure only Background Context Stack Level is Active by turning off
  647. * the Active bit in each of the other Executing Context Stack levels
  648. */
  649. ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
  650. IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
  651. ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
  652. ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0,
  653. ecsRegVal);
  654. ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
  655. IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
  656. ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
  657. ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0,
  658. ecsRegVal);
  659. ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
  660. IX_NPEDL_ECS_DBG_CTXT_REG_0);
  661. ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE;
  662. ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
  663. ecsRegVal);
  664. /* clear the pipeline */
  665. ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
  666. /* start NPE execution by issuing command through EXCTL register on NPE */
  667. ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START);
  668. /*
  669. * check execution status of NPE to verify NPE Start operation was
  670. * successful
  671. */
  672. npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress,
  673. IX_NPEDL_REG_OFFSET_EXCTL,
  674. IX_NPEDL_EXCTL_STATUS_RUN);
  675. if (npeRunning)
  676. {
  677. ixNpeDlNpeMgrStats.npeStarts++;
  678. }
  679. else
  680. {
  681. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: "
  682. "failed to start NPE execution\n");
  683. status = IX_FAIL;
  684. }
  685. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  686. "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status);
  687. return status;
  688. }
  689. /*
  690. * Function definition: ixNpeDlNpeMgrNpeStop
  691. */
  692. IX_STATUS
  693. ixNpeDlNpeMgrNpeStop (
  694. IxNpeDlNpeId npeId)
  695. {
  696. UINT32 npeBaseAddress;
  697. IX_STATUS status = IX_SUCCESS;
  698. IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
  699. "Entering ixNpeDlNpeMgrNpeStop\n");
  700. /* get base memory address of NPE from npeId */
  701. npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId);
  702. /* stop NPE execution by issuing command through EXCTL register on NPE */
  703. ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP);
  704. /* verify that NPE Stop was successful */
  705. if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL,
  706. IX_NPEDL_EXCTL_STATUS_STOP))
  707. {
  708. IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: "
  709. "failed to stop NPE execution\n");
  710. status = IX_FAIL;
  711. }
  712. ixNpeDlNpeMgrStats.npeStops++;
  713. IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
  714. "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status);
  715. return status;
  716. }
  717. /*
  718. * Function definition: ixNpeDlNpeMgrBitsSetCheck
  719. */
  720. PRIVATE BOOL
  721. ixNpeDlNpeMgrBitsSetCheck (
  722. UINT32 npeBaseAddress,
  723. UINT32 regOffset,
  724. UINT32 expectedBitsSet)
  725. {
  726. UINT32 regVal;
  727. IX_NPEDL_REG_READ (npeBaseAddress, regOffset, &regVal);
  728. return expectedBitsSet == (expectedBitsSet & regVal);
  729. }
  730. /*
  731. * Function definition: ixNpeDlNpeMgrStatsShow
  732. */
  733. void
  734. ixNpeDlNpeMgrStatsShow (void)
  735. {
  736. ixOsalLog (IX_OSAL_LOG_LVL_USER,
  737. IX_OSAL_LOG_DEV_STDOUT,
  738. "\nixNpeDlNpeMgrStatsShow:\n"
  739. "\tInstruction Blocks loaded: %u\n"
  740. "\tData Blocks loaded: %u\n"
  741. "\tState Information Blocks loaded: %u\n"
  742. "\tCritical NPE errors: %u\n"
  743. "\tCritical Microcode errors: %u\n",
  744. ixNpeDlNpeMgrStats.instructionBlocksLoaded,
  745. ixNpeDlNpeMgrStats.dataBlocksLoaded,
  746. ixNpeDlNpeMgrStats.stateInfoBlocksLoaded,
  747. ixNpeDlNpeMgrStats.criticalNpeErrors,
  748. ixNpeDlNpeMgrStats.criticalMicrocodeErrors,
  749. 0);
  750. ixOsalLog (IX_OSAL_LOG_LVL_USER,
  751. IX_OSAL_LOG_DEV_STDOUT,
  752. "\tSuccessful NPE Starts: %u\n"
  753. "\tSuccessful NPE Stops: %u\n"
  754. "\tSuccessful NPE Resets: %u\n\n",
  755. ixNpeDlNpeMgrStats.npeStarts,
  756. ixNpeDlNpeMgrStats.npeStops,
  757. ixNpeDlNpeMgrStats.npeResets,
  758. 0,0,0);
  759. ixNpeDlNpeMgrUtilsStatsShow ();
  760. }
  761. /*
  762. * Function definition: ixNpeDlNpeMgrStatsReset
  763. */
  764. void
  765. ixNpeDlNpeMgrStatsReset (void)
  766. {
  767. ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0;
  768. ixNpeDlNpeMgrStats.dataBlocksLoaded = 0;
  769. ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0;
  770. ixNpeDlNpeMgrStats.criticalNpeErrors = 0;
  771. ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0;
  772. ixNpeDlNpeMgrStats.npeStarts = 0;
  773. ixNpeDlNpeMgrStats.npeStops = 0;
  774. ixNpeDlNpeMgrStats.npeResets = 0;
  775. ixNpeDlNpeMgrUtilsStatsReset ();
  776. }