clk_rk3188.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dt-structs.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <mapmem.h>
  14. #include <syscon.h>
  15. #include <asm/io.h>
  16. #include <asm/arch-rockchip/clock.h>
  17. #include <asm/arch-rockchip/cru_rk3188.h>
  18. #include <asm/arch-rockchip/grf_rk3188.h>
  19. #include <asm/arch-rockchip/hardware.h>
  20. #include <dt-bindings/clock/rk3188-cru.h>
  21. #include <dm/device-internal.h>
  22. #include <dm/lists.h>
  23. #include <dm/uclass-internal.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <linux/log2.h>
  27. #include <linux/stringify.h>
  28. enum rk3188_clk_type {
  29. RK3188_CRU,
  30. RK3188A_CRU,
  31. };
  32. struct rk3188_clk_plat {
  33. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  34. struct dtd_rockchip_rk3188_cru dtd;
  35. #endif
  36. };
  37. struct pll_div {
  38. u32 nr;
  39. u32 nf;
  40. u32 no;
  41. };
  42. enum {
  43. VCO_MAX_HZ = 2200U * 1000000,
  44. VCO_MIN_HZ = 440 * 1000000,
  45. OUTPUT_MAX_HZ = 2200U * 1000000,
  46. OUTPUT_MIN_HZ = 30 * 1000000,
  47. FREF_MAX_HZ = 2200U * 1000000,
  48. FREF_MIN_HZ = 30 * 1000,
  49. };
  50. enum {
  51. /* PLL CON0 */
  52. PLL_OD_MASK = 0x0f,
  53. /* PLL CON1 */
  54. PLL_NF_MASK = 0x1fff,
  55. /* PLL CON2 */
  56. PLL_BWADJ_MASK = 0x0fff,
  57. /* PLL CON3 */
  58. PLL_RESET_SHIFT = 5,
  59. /* GRF_SOC_STATUS0 */
  60. SOCSTS_DPLL_LOCK = 1 << 5,
  61. SOCSTS_APLL_LOCK = 1 << 6,
  62. SOCSTS_CPLL_LOCK = 1 << 7,
  63. SOCSTS_GPLL_LOCK = 1 << 8,
  64. };
  65. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  66. #define PLL_DIVISORS(hz, _nr, _no) {\
  67. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  68. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  69. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  70. "divisors on line " __stringify(__LINE__));
  71. /* Keep divisors as low as possible to reduce jitter and power usage */
  72. #ifdef CONFIG_SPL_BUILD
  73. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  74. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  75. #endif
  76. static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id,
  77. const struct pll_div *div, bool has_bwadj)
  78. {
  79. int pll_id = rk_pll_id(clk_id);
  80. struct rk3188_pll *pll = &cru->pll[pll_id];
  81. /* All PLLs have same VCO and output frequency range restrictions. */
  82. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  83. uint output_hz = vco_hz / div->no;
  84. debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  85. (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  86. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  87. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
  88. (div->no == 1 || !(div->no % 2)));
  89. /* enter reset */
  90. rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  91. rk_clrsetreg(&pll->con0,
  92. CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
  93. ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
  94. rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
  95. if (has_bwadj)
  96. rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  97. udelay(10);
  98. /* return from reset */
  99. rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  100. return 0;
  101. }
  102. static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf,
  103. unsigned int hz, bool has_bwadj)
  104. {
  105. static const struct pll_div dpll_cfg[] = {
  106. {.nf = 75, .nr = 1, .no = 6},
  107. {.nf = 400, .nr = 9, .no = 2},
  108. {.nf = 500, .nr = 9, .no = 2},
  109. {.nf = 100, .nr = 3, .no = 1},
  110. };
  111. int cfg;
  112. switch (hz) {
  113. case 300000000:
  114. cfg = 0;
  115. break;
  116. case 533000000: /* actually 533.3P MHz */
  117. cfg = 1;
  118. break;
  119. case 666000000: /* actually 666.6P MHz */
  120. cfg = 2;
  121. break;
  122. case 800000000:
  123. cfg = 3;
  124. break;
  125. default:
  126. debug("Unsupported SDRAM frequency");
  127. return -EINVAL;
  128. }
  129. /* pll enter slow-mode */
  130. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  131. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  132. rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj);
  133. /* wait for pll lock */
  134. while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
  135. udelay(1);
  136. /* PLL enter normal-mode */
  137. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
  138. DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
  139. return 0;
  140. }
  141. static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf,
  142. unsigned int hz, bool has_bwadj)
  143. {
  144. static const struct pll_div apll_cfg[] = {
  145. {.nf = 50, .nr = 1, .no = 2},
  146. {.nf = 67, .nr = 1, .no = 1},
  147. };
  148. int div_core_peri, div_aclk_core, cfg;
  149. /*
  150. * We support two possible frequencies, the safe 600MHz
  151. * which will work with default pmic settings and will
  152. * be set in SPL to get away from the 24MHz default and
  153. * the maximum of 1.6Ghz, which boards can set if they
  154. * were able to get pmic support for it.
  155. */
  156. switch (hz) {
  157. case APLL_SAFE_HZ:
  158. cfg = 0;
  159. div_core_peri = 1;
  160. div_aclk_core = 3;
  161. break;
  162. case APLL_HZ:
  163. cfg = 1;
  164. div_core_peri = 2;
  165. div_aclk_core = 3;
  166. break;
  167. default:
  168. debug("Unsupported ARMCLK frequency");
  169. return -EINVAL;
  170. }
  171. /* pll enter slow-mode */
  172. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  173. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  174. rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj);
  175. /* waiting for pll lock */
  176. while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
  177. udelay(1);
  178. /* Set divider for peripherals attached to the cpu core. */
  179. rk_clrsetreg(&cru->cru_clksel_con[0],
  180. CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT,
  181. div_core_peri << CORE_PERI_DIV_SHIFT);
  182. /* set up dependent divisor for aclk_core */
  183. rk_clrsetreg(&cru->cru_clksel_con[1],
  184. CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT,
  185. div_aclk_core << CORE_ACLK_DIV_SHIFT);
  186. /* PLL enter normal-mode */
  187. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT,
  188. APLL_MODE_NORMAL << APLL_MODE_SHIFT);
  189. return hz;
  190. }
  191. /* Get pll rate by id */
  192. static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru,
  193. enum rk_clk_id clk_id)
  194. {
  195. uint32_t nr, no, nf;
  196. uint32_t con;
  197. int pll_id = rk_pll_id(clk_id);
  198. struct rk3188_pll *pll = &cru->pll[pll_id];
  199. static u8 clk_shift[CLK_COUNT] = {
  200. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  201. GPLL_MODE_SHIFT
  202. };
  203. uint shift;
  204. con = readl(&cru->cru_mode_con);
  205. shift = clk_shift[clk_id];
  206. switch ((con >> shift) & APLL_MODE_MASK) {
  207. case APLL_MODE_SLOW:
  208. return OSC_HZ;
  209. case APLL_MODE_NORMAL:
  210. /* normal mode */
  211. con = readl(&pll->con0);
  212. no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
  213. nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
  214. con = readl(&pll->con1);
  215. nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
  216. return (24 * nf / (nr * no)) * 1000000;
  217. case APLL_MODE_DEEP:
  218. default:
  219. return 32768;
  220. }
  221. }
  222. static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  223. int periph)
  224. {
  225. uint div;
  226. u32 con;
  227. switch (periph) {
  228. case HCLK_EMMC:
  229. case SCLK_EMMC:
  230. con = readl(&cru->cru_clksel_con[12]);
  231. div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
  232. break;
  233. case HCLK_SDMMC:
  234. case SCLK_SDMMC:
  235. con = readl(&cru->cru_clksel_con[11]);
  236. div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
  237. break;
  238. case HCLK_SDIO:
  239. case SCLK_SDIO:
  240. con = readl(&cru->cru_clksel_con[12]);
  241. div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
  242. break;
  243. default:
  244. return -EINVAL;
  245. }
  246. return DIV_TO_RATE(gclk_rate, div) / 2;
  247. }
  248. static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  249. int periph, uint freq)
  250. {
  251. int src_clk_div;
  252. debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
  253. /* mmc clock defaulg div 2 internal, need provide double in cru */
  254. src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
  255. assert(src_clk_div <= 0x3f);
  256. switch (periph) {
  257. case HCLK_EMMC:
  258. case SCLK_EMMC:
  259. rk_clrsetreg(&cru->cru_clksel_con[12],
  260. EMMC_DIV_MASK << EMMC_DIV_SHIFT,
  261. src_clk_div << EMMC_DIV_SHIFT);
  262. break;
  263. case HCLK_SDMMC:
  264. case SCLK_SDMMC:
  265. rk_clrsetreg(&cru->cru_clksel_con[11],
  266. MMC0_DIV_MASK << MMC0_DIV_SHIFT,
  267. src_clk_div << MMC0_DIV_SHIFT);
  268. break;
  269. case HCLK_SDIO:
  270. case SCLK_SDIO:
  271. rk_clrsetreg(&cru->cru_clksel_con[12],
  272. SDIO_DIV_MASK << SDIO_DIV_SHIFT,
  273. src_clk_div << SDIO_DIV_SHIFT);
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. return rockchip_mmc_get_clk(cru, gclk_rate, periph);
  279. }
  280. static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
  281. int periph)
  282. {
  283. uint div;
  284. u32 con;
  285. switch (periph) {
  286. case SCLK_SPI0:
  287. con = readl(&cru->cru_clksel_con[25]);
  288. div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
  289. break;
  290. case SCLK_SPI1:
  291. con = readl(&cru->cru_clksel_con[25]);
  292. div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
  293. break;
  294. default:
  295. return -EINVAL;
  296. }
  297. return DIV_TO_RATE(gclk_rate, div);
  298. }
  299. static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
  300. int periph, uint freq)
  301. {
  302. int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
  303. assert(src_clk_div < 128);
  304. switch (periph) {
  305. case SCLK_SPI0:
  306. assert(src_clk_div <= SPI0_DIV_MASK);
  307. rk_clrsetreg(&cru->cru_clksel_con[25],
  308. SPI0_DIV_MASK << SPI0_DIV_SHIFT,
  309. src_clk_div << SPI0_DIV_SHIFT);
  310. break;
  311. case SCLK_SPI1:
  312. assert(src_clk_div <= SPI1_DIV_MASK);
  313. rk_clrsetreg(&cru->cru_clksel_con[25],
  314. SPI1_DIV_MASK << SPI1_DIV_SHIFT,
  315. src_clk_div << SPI1_DIV_SHIFT);
  316. break;
  317. default:
  318. return -EINVAL;
  319. }
  320. return rockchip_spi_get_clk(cru, gclk_rate, periph);
  321. }
  322. #ifdef CONFIG_SPL_BUILD
  323. static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
  324. bool has_bwadj)
  325. {
  326. u32 aclk_div, hclk_div, pclk_div, h2p_div;
  327. /* pll enter slow-mode */
  328. rk_clrsetreg(&cru->cru_mode_con,
  329. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  330. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  331. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  332. CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
  333. /* init pll */
  334. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
  335. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj);
  336. /* waiting for pll lock */
  337. while ((readl(&grf->soc_status0) &
  338. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
  339. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
  340. udelay(1);
  341. /*
  342. * cpu clock pll source selection and
  343. * reparent aclk_cpu_pre from apll to gpll
  344. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  345. */
  346. aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
  347. assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  348. rk_clrsetreg(&cru->cru_clksel_con[0],
  349. CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
  350. A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT,
  351. CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
  352. aclk_div << A9_CPU_DIV_SHIFT);
  353. hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
  354. assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
  355. pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
  356. assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
  357. h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
  358. assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
  359. rk_clrsetreg(&cru->cru_clksel_con[1],
  360. AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT |
  361. CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT |
  362. CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT,
  363. h2p_div << AHB2APB_DIV_SHIFT |
  364. pclk_div << CPU_PCLK_DIV_SHIFT |
  365. hclk_div << CPU_HCLK_DIV_SHIFT);
  366. /*
  367. * peri clock pll source selection and
  368. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  369. */
  370. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  371. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  372. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  373. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  374. PERI_ACLK_HZ && (hclk_div < 0x4));
  375. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  376. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  377. PERI_ACLK_HZ && (pclk_div < 0x4));
  378. rk_clrsetreg(&cru->cru_clksel_con[10],
  379. PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
  380. PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
  381. PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
  382. PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
  383. pclk_div << PERI_PCLK_DIV_SHIFT |
  384. hclk_div << PERI_HCLK_DIV_SHIFT |
  385. aclk_div << PERI_ACLK_DIV_SHIFT);
  386. /* PLL enter normal-mode */
  387. rk_clrsetreg(&cru->cru_mode_con,
  388. GPLL_MODE_MASK << GPLL_MODE_SHIFT |
  389. CPLL_MODE_MASK << CPLL_MODE_SHIFT,
  390. GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
  391. CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
  392. rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
  393. }
  394. #endif
  395. static ulong rk3188_clk_get_rate(struct clk *clk)
  396. {
  397. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  398. ulong new_rate, gclk_rate;
  399. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  400. switch (clk->id) {
  401. case 1 ... 4:
  402. new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
  403. break;
  404. case HCLK_EMMC:
  405. case HCLK_SDMMC:
  406. case HCLK_SDIO:
  407. case SCLK_EMMC:
  408. case SCLK_SDMMC:
  409. case SCLK_SDIO:
  410. new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
  411. clk->id);
  412. break;
  413. case SCLK_SPI0:
  414. case SCLK_SPI1:
  415. new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ,
  416. clk->id);
  417. break;
  418. case PCLK_I2C0:
  419. case PCLK_I2C1:
  420. case PCLK_I2C2:
  421. case PCLK_I2C3:
  422. case PCLK_I2C4:
  423. return gclk_rate;
  424. default:
  425. return -ENOENT;
  426. }
  427. return new_rate;
  428. }
  429. static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
  430. {
  431. struct rk3188_clk_priv *priv = dev_get_priv(clk->dev);
  432. struct rk3188_cru *cru = priv->cru;
  433. ulong new_rate;
  434. switch (clk->id) {
  435. case PLL_APLL:
  436. new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate,
  437. priv->has_bwadj);
  438. break;
  439. case CLK_DDR:
  440. new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate,
  441. priv->has_bwadj);
  442. break;
  443. case HCLK_EMMC:
  444. case HCLK_SDMMC:
  445. case HCLK_SDIO:
  446. case SCLK_EMMC:
  447. case SCLK_SDMMC:
  448. case SCLK_SDIO:
  449. new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
  450. clk->id, rate);
  451. break;
  452. case SCLK_SPI0:
  453. case SCLK_SPI1:
  454. new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ,
  455. clk->id, rate);
  456. break;
  457. default:
  458. return -ENOENT;
  459. }
  460. return new_rate;
  461. }
  462. static struct clk_ops rk3188_clk_ops = {
  463. .get_rate = rk3188_clk_get_rate,
  464. .set_rate = rk3188_clk_set_rate,
  465. };
  466. static int rk3188_clk_ofdata_to_platdata(struct udevice *dev)
  467. {
  468. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  469. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  470. priv->cru = dev_read_addr_ptr(dev);
  471. #endif
  472. return 0;
  473. }
  474. static int rk3188_clk_probe(struct udevice *dev)
  475. {
  476. struct rk3188_clk_priv *priv = dev_get_priv(dev);
  477. enum rk3188_clk_type type = dev_get_driver_data(dev);
  478. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  479. if (IS_ERR(priv->grf))
  480. return PTR_ERR(priv->grf);
  481. priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
  482. #ifdef CONFIG_SPL_BUILD
  483. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  484. struct rk3188_clk_plat *plat = dev_get_platdata(dev);
  485. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  486. #endif
  487. rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
  488. /* Init CPU frequency */
  489. rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ,
  490. priv->has_bwadj);
  491. #endif
  492. return 0;
  493. }
  494. static int rk3188_clk_bind(struct udevice *dev)
  495. {
  496. int ret;
  497. struct udevice *sys_child;
  498. struct sysreset_reg *priv;
  499. /* The reset driver does not have a device node, so bind it here */
  500. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  501. &sys_child);
  502. if (ret) {
  503. debug("Warning: No sysreset driver: ret=%d\n", ret);
  504. } else {
  505. priv = malloc(sizeof(struct sysreset_reg));
  506. priv->glb_srst_fst_value = offsetof(struct rk3188_cru,
  507. cru_glb_srst_fst_value);
  508. priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
  509. cru_glb_srst_snd_value);
  510. sys_child->priv = priv;
  511. }
  512. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  513. ret = offsetof(struct rk3188_cru, cru_softrst_con[0]);
  514. ret = rockchip_reset_bind(dev, ret, 9);
  515. if (ret)
  516. debug("Warning: software reset driver bind faile\n");
  517. #endif
  518. return 0;
  519. }
  520. static const struct udevice_id rk3188_clk_ids[] = {
  521. { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU },
  522. { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU },
  523. { }
  524. };
  525. U_BOOT_DRIVER(rockchip_rk3188_cru) = {
  526. .name = "rockchip_rk3188_cru",
  527. .id = UCLASS_CLK,
  528. .of_match = rk3188_clk_ids,
  529. .priv_auto = sizeof(struct rk3188_clk_priv),
  530. .plat_auto = sizeof(struct rk3188_clk_plat),
  531. .ops = &rk3188_clk_ops,
  532. .bind = rk3188_clk_bind,
  533. .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata,
  534. .probe = rk3188_clk_probe,
  535. };