clk_fixed_rate.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <linux/clk-provider.h>
  9. static ulong clk_fixed_rate_get_rate(struct clk *clk)
  10. {
  11. return to_clk_fixed_rate(clk->dev)->fixed_rate;
  12. }
  13. /* avoid clk_enable() return -ENOSYS */
  14. static int dummy_enable(struct clk *clk)
  15. {
  16. return 0;
  17. }
  18. const struct clk_ops clk_fixed_rate_ops = {
  19. .get_rate = clk_fixed_rate_get_rate,
  20. .enable = dummy_enable,
  21. };
  22. static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
  23. {
  24. struct clk *clk = &to_clk_fixed_rate(dev)->clk;
  25. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  26. to_clk_fixed_rate(dev)->fixed_rate =
  27. dev_read_u32_default(dev, "clock-frequency", 0);
  28. #endif
  29. /* Make fixed rate clock accessible from higher level struct clk */
  30. dev->uclass_priv = clk;
  31. clk->dev = dev;
  32. clk->enable_count = 0;
  33. return 0;
  34. }
  35. static const struct udevice_id clk_fixed_rate_match[] = {
  36. {
  37. .compatible = "fixed-clock",
  38. },
  39. { /* sentinel */ }
  40. };
  41. U_BOOT_DRIVER(fixed_clock) = {
  42. .name = "fixed_clock",
  43. .id = UCLASS_CLK,
  44. .of_match = clk_fixed_rate_match,
  45. .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
  46. .plat_auto = sizeof(struct clk_fixed_rate),
  47. .ops = &clk_fixed_rate_ops,
  48. .flags = DM_FLAG_PRE_RELOC,
  49. };