compat.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Compatible code for non CCF AT91 platforms.
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/lists.h>
  14. #include <dm/util.h>
  15. #include <mach/at91_pmc.h>
  16. #include <mach/at91_sfr.h>
  17. #include <regmap.h>
  18. #include <syscon.h>
  19. #include "pmc.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. struct pmc_platdata {
  22. struct at91_pmc *reg_base;
  23. struct regmap *regmap_sfr;
  24. };
  25. static const struct udevice_id at91_pmc_match[] = {
  26. { .compatible = "atmel,at91rm9200-pmc" },
  27. { .compatible = "atmel,at91sam9260-pmc" },
  28. { .compatible = "atmel,at91sam9g45-pmc" },
  29. { .compatible = "atmel,at91sam9n12-pmc" },
  30. { .compatible = "atmel,at91sam9x5-pmc" },
  31. { .compatible = "atmel,sama5d3-pmc" },
  32. { .compatible = "atmel,sama5d2-pmc" },
  33. {}
  34. };
  35. U_BOOT_DRIVER(at91_pmc) = {
  36. .name = "at91-pmc",
  37. .id = UCLASS_SIMPLE_BUS,
  38. .of_match = at91_pmc_match,
  39. };
  40. static int at91_pmc_core_probe(struct udevice *dev)
  41. {
  42. struct pmc_platdata *plat = dev_get_platdata(dev);
  43. dev = dev_get_parent(dev);
  44. plat->reg_base = dev_read_addr_ptr(dev);
  45. return 0;
  46. }
  47. /**
  48. * at91_clk_sub_device_bind() - for the at91 clock driver
  49. * Recursively bind its children as clk devices.
  50. *
  51. * @return: 0 on success, or negative error code on failure
  52. */
  53. int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  54. {
  55. ofnode parent = dev_ofnode(dev);
  56. ofnode node;
  57. bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  58. const char *name;
  59. int ret;
  60. ofnode_for_each_subnode(node, parent) {
  61. if (pre_reloc_only && !ofnode_pre_reloc(node))
  62. continue;
  63. /*
  64. * If this node has "compatible" property, this is not
  65. * a clock sub-node, but a normal device. skip.
  66. */
  67. if (ofnode_read_prop(node, "compatible", NULL))
  68. continue;
  69. if (ret != -FDT_ERR_NOTFOUND)
  70. return ret;
  71. name = ofnode_get_name(node);
  72. if (!name)
  73. return -EINVAL;
  74. ret = device_bind_driver_to_node(dev, drv_name, name, node,
  75. NULL);
  76. if (ret)
  77. return ret;
  78. }
  79. return 0;
  80. }
  81. int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  82. {
  83. int periph;
  84. if (args->args_count) {
  85. debug("Invalid args_count: %d\n", args->args_count);
  86. return -EINVAL;
  87. }
  88. periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
  89. -1);
  90. if (periph < 0)
  91. return -EINVAL;
  92. clk->id = periph;
  93. return 0;
  94. }
  95. int at91_clk_probe(struct udevice *dev)
  96. {
  97. struct udevice *dev_periph_container, *dev_pmc;
  98. struct pmc_platdata *plat = dev_get_platdata(dev);
  99. dev_periph_container = dev_get_parent(dev);
  100. dev_pmc = dev_get_parent(dev_periph_container);
  101. plat->reg_base = dev_read_addr_ptr(dev_pmc);
  102. return 0;
  103. }
  104. /* SCKC specific code. */
  105. static const struct udevice_id at91_sckc_match[] = {
  106. { .compatible = "atmel,at91sam9x5-sckc" },
  107. {}
  108. };
  109. U_BOOT_DRIVER(at91_sckc) = {
  110. .name = "at91-sckc",
  111. .id = UCLASS_SIMPLE_BUS,
  112. .of_match = at91_sckc_match,
  113. };
  114. /* Slow clock specific code. */
  115. static int at91_slow_clk_enable(struct clk *clk)
  116. {
  117. return 0;
  118. }
  119. static ulong at91_slow_clk_get_rate(struct clk *clk)
  120. {
  121. return CONFIG_SYS_AT91_SLOW_CLOCK;
  122. }
  123. static struct clk_ops at91_slow_clk_ops = {
  124. .enable = at91_slow_clk_enable,
  125. .get_rate = at91_slow_clk_get_rate,
  126. };
  127. static const struct udevice_id at91_slow_clk_match[] = {
  128. { .compatible = "atmel,at91sam9x5-clk-slow" },
  129. {}
  130. };
  131. U_BOOT_DRIVER(at91_slow_clk) = {
  132. .name = "at91-slow-clk",
  133. .id = UCLASS_CLK,
  134. .of_match = at91_slow_clk_match,
  135. .ops = &at91_slow_clk_ops,
  136. };
  137. /* Master clock specific code. */
  138. static ulong at91_master_clk_get_rate(struct clk *clk)
  139. {
  140. return gd->arch.mck_rate_hz;
  141. }
  142. static struct clk_ops at91_master_clk_ops = {
  143. .get_rate = at91_master_clk_get_rate,
  144. };
  145. static const struct udevice_id at91_master_clk_match[] = {
  146. { .compatible = "atmel,at91rm9200-clk-master" },
  147. { .compatible = "atmel,at91sam9x5-clk-master" },
  148. {}
  149. };
  150. U_BOOT_DRIVER(at91_master_clk) = {
  151. .name = "at91-master-clk",
  152. .id = UCLASS_CLK,
  153. .of_match = at91_master_clk_match,
  154. .ops = &at91_master_clk_ops,
  155. };
  156. /* Main osc clock specific code. */
  157. static int main_osc_clk_enable(struct clk *clk)
  158. {
  159. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  160. struct at91_pmc *pmc = plat->reg_base;
  161. if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
  162. return 0;
  163. return -EINVAL;
  164. }
  165. static ulong main_osc_clk_get_rate(struct clk *clk)
  166. {
  167. return gd->arch.main_clk_rate_hz;
  168. }
  169. static struct clk_ops main_osc_clk_ops = {
  170. .enable = main_osc_clk_enable,
  171. .get_rate = main_osc_clk_get_rate,
  172. };
  173. static int main_osc_clk_probe(struct udevice *dev)
  174. {
  175. return at91_pmc_core_probe(dev);
  176. }
  177. static const struct udevice_id main_osc_clk_match[] = {
  178. { .compatible = "atmel,at91sam9x5-clk-main" },
  179. {}
  180. };
  181. U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
  182. .name = "at91sam9x5-main-osc-clk",
  183. .id = UCLASS_CLK,
  184. .of_match = main_osc_clk_match,
  185. .probe = main_osc_clk_probe,
  186. .plat_auto = sizeof(struct pmc_platdata),
  187. .ops = &main_osc_clk_ops,
  188. };
  189. /* PLLA clock specific code. */
  190. static int plla_clk_enable(struct clk *clk)
  191. {
  192. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  193. struct at91_pmc *pmc = plat->reg_base;
  194. if (readl(&pmc->sr) & AT91_PMC_LOCKA)
  195. return 0;
  196. return -EINVAL;
  197. }
  198. static ulong plla_clk_get_rate(struct clk *clk)
  199. {
  200. return gd->arch.plla_rate_hz;
  201. }
  202. static struct clk_ops plla_clk_ops = {
  203. .enable = plla_clk_enable,
  204. .get_rate = plla_clk_get_rate,
  205. };
  206. static int plla_clk_probe(struct udevice *dev)
  207. {
  208. return at91_pmc_core_probe(dev);
  209. }
  210. static const struct udevice_id plla_clk_match[] = {
  211. { .compatible = "atmel,sama5d3-clk-pll" },
  212. {}
  213. };
  214. U_BOOT_DRIVER(at91_plla_clk) = {
  215. .name = "at91-plla-clk",
  216. .id = UCLASS_CLK,
  217. .of_match = plla_clk_match,
  218. .probe = plla_clk_probe,
  219. .plat_auto = sizeof(struct pmc_platdata),
  220. .ops = &plla_clk_ops,
  221. };
  222. /* PLLA DIV clock specific code. */
  223. static int at91_plladiv_clk_enable(struct clk *clk)
  224. {
  225. return 0;
  226. }
  227. static ulong at91_plladiv_clk_get_rate(struct clk *clk)
  228. {
  229. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  230. struct at91_pmc *pmc = plat->reg_base;
  231. struct clk source;
  232. ulong clk_rate;
  233. int ret;
  234. ret = clk_get_by_index(clk->dev, 0, &source);
  235. if (ret)
  236. return -EINVAL;
  237. clk_rate = clk_get_rate(&source);
  238. if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
  239. clk_rate /= 2;
  240. return clk_rate;
  241. }
  242. static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
  243. {
  244. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  245. struct at91_pmc *pmc = plat->reg_base;
  246. struct clk source;
  247. ulong parent_rate;
  248. int ret;
  249. ret = clk_get_by_index(clk->dev, 0, &source);
  250. if (ret)
  251. return -EINVAL;
  252. parent_rate = clk_get_rate(&source);
  253. if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
  254. return -EINVAL;
  255. if (parent_rate != rate) {
  256. writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
  257. &pmc->mckr);
  258. }
  259. return 0;
  260. }
  261. static struct clk_ops at91_plladiv_clk_ops = {
  262. .enable = at91_plladiv_clk_enable,
  263. .get_rate = at91_plladiv_clk_get_rate,
  264. .set_rate = at91_plladiv_clk_set_rate,
  265. };
  266. static int at91_plladiv_clk_probe(struct udevice *dev)
  267. {
  268. return at91_pmc_core_probe(dev);
  269. }
  270. static const struct udevice_id at91_plladiv_clk_match[] = {
  271. { .compatible = "atmel,at91sam9x5-clk-plldiv" },
  272. {}
  273. };
  274. U_BOOT_DRIVER(at91_plladiv_clk) = {
  275. .name = "at91-plladiv-clk",
  276. .id = UCLASS_CLK,
  277. .of_match = at91_plladiv_clk_match,
  278. .probe = at91_plladiv_clk_probe,
  279. .plat_auto = sizeof(struct pmc_platdata),
  280. .ops = &at91_plladiv_clk_ops,
  281. };
  282. /* System clock specific code. */
  283. #define SYSTEM_MAX_ID 31
  284. /**
  285. * at91_system_clk_bind() - for the system clock driver
  286. * Recursively bind its children as clk devices.
  287. *
  288. * @return: 0 on success, or negative error code on failure
  289. */
  290. static int at91_system_clk_bind(struct udevice *dev)
  291. {
  292. return at91_clk_sub_device_bind(dev, "system-clk");
  293. }
  294. static const struct udevice_id at91_system_clk_match[] = {
  295. { .compatible = "atmel,at91rm9200-clk-system" },
  296. {}
  297. };
  298. U_BOOT_DRIVER(at91_system_clk) = {
  299. .name = "at91-system-clk",
  300. .id = UCLASS_MISC,
  301. .of_match = at91_system_clk_match,
  302. .bind = at91_system_clk_bind,
  303. };
  304. static inline int is_pck(int id)
  305. {
  306. return (id >= 8) && (id <= 15);
  307. }
  308. static ulong system_clk_get_rate(struct clk *clk)
  309. {
  310. struct clk clk_dev;
  311. int ret;
  312. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  313. if (ret)
  314. return -EINVAL;
  315. return clk_get_rate(&clk_dev);
  316. }
  317. static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  318. {
  319. struct clk clk_dev;
  320. int ret;
  321. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  322. if (ret)
  323. return -EINVAL;
  324. return clk_set_rate(&clk_dev, rate);
  325. }
  326. static int system_clk_enable(struct clk *clk)
  327. {
  328. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  329. struct at91_pmc *pmc = plat->reg_base;
  330. u32 mask;
  331. if (clk->id > SYSTEM_MAX_ID)
  332. return -EINVAL;
  333. mask = BIT(clk->id);
  334. writel(mask, &pmc->scer);
  335. /**
  336. * For the programmable clocks the Ready status in the PMC
  337. * status register should be checked after enabling.
  338. * For other clocks this is unnecessary.
  339. */
  340. if (!is_pck(clk->id))
  341. return 0;
  342. while (!(readl(&pmc->sr) & mask))
  343. ;
  344. return 0;
  345. }
  346. static struct clk_ops system_clk_ops = {
  347. .of_xlate = at91_clk_of_xlate,
  348. .get_rate = system_clk_get_rate,
  349. .set_rate = system_clk_set_rate,
  350. .enable = system_clk_enable,
  351. };
  352. U_BOOT_DRIVER(system_clk) = {
  353. .name = "system-clk",
  354. .id = UCLASS_CLK,
  355. .probe = at91_clk_probe,
  356. .plat_auto = sizeof(struct pmc_platdata),
  357. .ops = &system_clk_ops,
  358. };
  359. /* Peripheral clock specific code. */
  360. #define PERIPHERAL_ID_MIN 2
  361. #define PERIPHERAL_ID_MAX 31
  362. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  363. enum periph_clk_type {
  364. CLK_PERIPH_AT91RM9200 = 0,
  365. CLK_PERIPH_AT91SAM9X5,
  366. };
  367. /**
  368. * sam9x5_periph_clk_bind() - for the periph clock driver
  369. * Recursively bind its children as clk devices.
  370. *
  371. * @return: 0 on success, or negative error code on failure
  372. */
  373. static int sam9x5_periph_clk_bind(struct udevice *dev)
  374. {
  375. return at91_clk_sub_device_bind(dev, "periph-clk");
  376. }
  377. static const struct udevice_id sam9x5_periph_clk_match[] = {
  378. {
  379. .compatible = "atmel,at91rm9200-clk-peripheral",
  380. .data = CLK_PERIPH_AT91RM9200,
  381. },
  382. {
  383. .compatible = "atmel,at91sam9x5-clk-peripheral",
  384. .data = CLK_PERIPH_AT91SAM9X5,
  385. },
  386. {}
  387. };
  388. U_BOOT_DRIVER(sam9x5_periph_clk) = {
  389. .name = "sam9x5-periph-clk",
  390. .id = UCLASS_MISC,
  391. .of_match = sam9x5_periph_clk_match,
  392. .bind = sam9x5_periph_clk_bind,
  393. };
  394. static int periph_clk_enable(struct clk *clk)
  395. {
  396. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  397. struct at91_pmc *pmc = plat->reg_base;
  398. enum periph_clk_type clk_type;
  399. void *addr;
  400. if (clk->id < PERIPHERAL_ID_MIN)
  401. return -1;
  402. clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
  403. if (clk_type == CLK_PERIPH_AT91RM9200) {
  404. addr = &pmc->pcer;
  405. if (clk->id > PERIPHERAL_ID_MAX)
  406. addr = &pmc->pcer1;
  407. setbits_le32(addr, PERIPHERAL_MASK(clk->id));
  408. } else {
  409. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  410. setbits_le32(&pmc->pcr,
  411. AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
  412. }
  413. return 0;
  414. }
  415. static ulong periph_get_rate(struct clk *clk)
  416. {
  417. struct udevice *dev;
  418. struct clk clk_dev;
  419. ulong clk_rate;
  420. int ret;
  421. dev = dev_get_parent(clk->dev);
  422. ret = clk_get_by_index(dev, 0, &clk_dev);
  423. if (ret)
  424. return ret;
  425. clk_rate = clk_get_rate(&clk_dev);
  426. clk_free(&clk_dev);
  427. return clk_rate;
  428. }
  429. static struct clk_ops periph_clk_ops = {
  430. .of_xlate = at91_clk_of_xlate,
  431. .enable = periph_clk_enable,
  432. .get_rate = periph_get_rate,
  433. };
  434. U_BOOT_DRIVER(clk_periph) = {
  435. .name = "periph-clk",
  436. .id = UCLASS_CLK,
  437. .plat_auto = sizeof(struct pmc_platdata),
  438. .probe = at91_clk_probe,
  439. .ops = &periph_clk_ops,
  440. };
  441. /* UTMI clock specific code. */
  442. #ifdef CONFIG_AT91_UTMI
  443. /*
  444. * The purpose of this clock is to generate a 480 MHz signal. A different
  445. * rate can't be configured.
  446. */
  447. #define UTMI_RATE 480000000
  448. static int utmi_clk_enable(struct clk *clk)
  449. {
  450. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  451. struct at91_pmc *pmc = plat->reg_base;
  452. struct clk clk_dev;
  453. ulong clk_rate;
  454. u32 utmi_ref_clk_freq;
  455. u32 tmp;
  456. int err;
  457. int timeout = 2000000;
  458. if (readl(&pmc->sr) & AT91_PMC_LOCKU)
  459. return 0;
  460. /*
  461. * If mainck rate is different from 12 MHz, we have to configure the
  462. * FREQ field of the SFR_UTMICKTRIM register to generate properly
  463. * the utmi clock.
  464. */
  465. err = clk_get_by_index(clk->dev, 0, &clk_dev);
  466. if (err)
  467. return -EINVAL;
  468. clk_rate = clk_get_rate(&clk_dev);
  469. switch (clk_rate) {
  470. case 12000000:
  471. utmi_ref_clk_freq = 0;
  472. break;
  473. case 16000000:
  474. utmi_ref_clk_freq = 1;
  475. break;
  476. case 24000000:
  477. utmi_ref_clk_freq = 2;
  478. break;
  479. /*
  480. * Not supported on SAMA5D2 but it's not an issue since MAINCK
  481. * maximum value is 24 MHz.
  482. */
  483. case 48000000:
  484. utmi_ref_clk_freq = 3;
  485. break;
  486. default:
  487. printf("UTMICK: unsupported mainck rate\n");
  488. return -EINVAL;
  489. }
  490. if (plat->regmap_sfr) {
  491. err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
  492. if (err)
  493. return -EINVAL;
  494. tmp &= ~AT91_UTMICKTRIM_FREQ;
  495. tmp |= utmi_ref_clk_freq;
  496. err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
  497. if (err)
  498. return -EINVAL;
  499. } else if (utmi_ref_clk_freq) {
  500. printf("UTMICK: sfr node required\n");
  501. return -EINVAL;
  502. }
  503. tmp = readl(&pmc->uckr);
  504. tmp |= AT91_PMC_UPLLEN |
  505. AT91_PMC_UPLLCOUNT |
  506. AT91_PMC_BIASEN;
  507. writel(tmp, &pmc->uckr);
  508. while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
  509. ;
  510. if (!timeout) {
  511. printf("UTMICK: timeout waiting for UPLL lock\n");
  512. return -ETIMEDOUT;
  513. }
  514. return 0;
  515. }
  516. static ulong utmi_clk_get_rate(struct clk *clk)
  517. {
  518. /* UTMI clk rate is fixed. */
  519. return UTMI_RATE;
  520. }
  521. static struct clk_ops utmi_clk_ops = {
  522. .enable = utmi_clk_enable,
  523. .get_rate = utmi_clk_get_rate,
  524. };
  525. static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
  526. {
  527. struct pmc_platdata *plat = dev_get_platdata(dev);
  528. struct udevice *syscon;
  529. uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  530. "regmap-sfr", &syscon);
  531. if (syscon)
  532. plat->regmap_sfr = syscon_get_regmap(syscon);
  533. return 0;
  534. }
  535. static int utmi_clk_probe(struct udevice *dev)
  536. {
  537. return at91_pmc_core_probe(dev);
  538. }
  539. static const struct udevice_id utmi_clk_match[] = {
  540. { .compatible = "atmel,at91sam9x5-clk-utmi" },
  541. {}
  542. };
  543. U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
  544. .name = "at91sam9x5-utmi-clk",
  545. .id = UCLASS_CLK,
  546. .of_match = utmi_clk_match,
  547. .probe = utmi_clk_probe,
  548. .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
  549. .plat_auto = sizeof(struct pmc_platdata),
  550. .ops = &utmi_clk_ops,
  551. };
  552. #endif /* CONFIG_AT91_UTMI */
  553. /* H32MX clock specific code. */
  554. #ifdef CONFIG_AT91_H32MX
  555. #define H32MX_MAX_FREQ 90000000
  556. static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
  557. {
  558. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  559. struct at91_pmc *pmc = plat->reg_base;
  560. ulong rate = gd->arch.mck_rate_hz;
  561. if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
  562. rate /= 2;
  563. if (rate > H32MX_MAX_FREQ)
  564. dev_dbg(clk->dev, "H32MX clock is too fast\n");
  565. return rate;
  566. }
  567. static struct clk_ops sama5d4_h32mx_clk_ops = {
  568. .get_rate = sama5d4_h32mx_clk_get_rate,
  569. };
  570. static int sama5d4_h32mx_clk_probe(struct udevice *dev)
  571. {
  572. return at91_pmc_core_probe(dev);
  573. }
  574. static const struct udevice_id sama5d4_h32mx_clk_match[] = {
  575. { .compatible = "atmel,sama5d4-clk-h32mx" },
  576. {}
  577. };
  578. U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
  579. .name = "sama5d4-h32mx-clk",
  580. .id = UCLASS_CLK,
  581. .of_match = sama5d4_h32mx_clk_match,
  582. .probe = sama5d4_h32mx_clk_probe,
  583. .plat_auto = sizeof(struct pmc_platdata),
  584. .ops = &sama5d4_h32mx_clk_ops,
  585. };
  586. #endif /* CONFIG_AT91_H32MX */
  587. /* Generic clock specific code. */
  588. #ifdef CONFIG_AT91_GENERIC_CLK
  589. #define GENERATED_SOURCE_MAX 6
  590. #define GENERATED_MAX_DIV 255
  591. /**
  592. * generated_clk_bind() - for the generated clock driver
  593. * Recursively bind its children as clk devices.
  594. *
  595. * @return: 0 on success, or negative error code on failure
  596. */
  597. static int generated_clk_bind(struct udevice *dev)
  598. {
  599. return at91_clk_sub_device_bind(dev, "generic-clk");
  600. }
  601. static const struct udevice_id generated_clk_match[] = {
  602. { .compatible = "atmel,sama5d2-clk-generated" },
  603. {}
  604. };
  605. U_BOOT_DRIVER(generated_clk) = {
  606. .name = "generated-clk",
  607. .id = UCLASS_MISC,
  608. .of_match = generated_clk_match,
  609. .bind = generated_clk_bind,
  610. };
  611. struct generic_clk_priv {
  612. u32 num_parents;
  613. };
  614. static ulong generic_clk_get_rate(struct clk *clk)
  615. {
  616. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  617. struct at91_pmc *pmc = plat->reg_base;
  618. struct clk parent;
  619. ulong clk_rate;
  620. u32 tmp, gckdiv;
  621. u8 clock_source, parent_index;
  622. int ret;
  623. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  624. tmp = readl(&pmc->pcr);
  625. clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
  626. AT91_PMC_PCR_GCKCSS_MASK;
  627. gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
  628. parent_index = clock_source - 1;
  629. ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
  630. if (ret)
  631. return 0;
  632. clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
  633. clk_free(&parent);
  634. return clk_rate;
  635. }
  636. static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
  637. {
  638. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  639. struct at91_pmc *pmc = plat->reg_base;
  640. struct generic_clk_priv *priv = dev_get_priv(clk->dev);
  641. struct clk parent, best_parent;
  642. ulong tmp_rate, best_rate = rate, parent_rate;
  643. int tmp_diff, best_diff = -1;
  644. u32 div, best_div = 0;
  645. u8 best_parent_index, best_clock_source = 0;
  646. u8 i;
  647. u32 tmp;
  648. int ret;
  649. for (i = 0; i < priv->num_parents; i++) {
  650. ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
  651. if (ret)
  652. return ret;
  653. parent_rate = clk_get_rate(&parent);
  654. if (IS_ERR_VALUE(parent_rate))
  655. return parent_rate;
  656. for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
  657. tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
  658. tmp_diff = abs(rate - tmp_rate);
  659. if (best_diff < 0 || best_diff > tmp_diff) {
  660. best_rate = tmp_rate;
  661. best_diff = tmp_diff;
  662. best_div = div - 1;
  663. best_parent = parent;
  664. best_parent_index = i;
  665. best_clock_source = best_parent_index + 1;
  666. }
  667. if (!best_diff || tmp_rate < rate)
  668. break;
  669. }
  670. if (!best_diff)
  671. break;
  672. }
  673. debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
  674. best_parent.dev->name, best_rate, best_div);
  675. ret = clk_enable(&best_parent);
  676. if (ret)
  677. return ret;
  678. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  679. tmp = readl(&pmc->pcr);
  680. tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
  681. tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
  682. AT91_PMC_PCR_CMD_WRITE |
  683. AT91_PMC_PCR_GCKDIV_(best_div) |
  684. AT91_PMC_PCR_GCKEN;
  685. writel(tmp, &pmc->pcr);
  686. while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
  687. ;
  688. return 0;
  689. }
  690. static struct clk_ops generic_clk_ops = {
  691. .of_xlate = at91_clk_of_xlate,
  692. .get_rate = generic_clk_get_rate,
  693. .set_rate = generic_clk_set_rate,
  694. };
  695. static int generic_clk_ofdata_to_platdata(struct udevice *dev)
  696. {
  697. struct generic_clk_priv *priv = dev_get_priv(dev);
  698. u32 cells[GENERATED_SOURCE_MAX];
  699. u32 num_parents;
  700. num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
  701. dev_of_offset(dev_get_parent(dev)), "clocks", cells,
  702. GENERATED_SOURCE_MAX);
  703. if (!num_parents)
  704. return -1;
  705. priv->num_parents = num_parents;
  706. return 0;
  707. }
  708. U_BOOT_DRIVER(generic_clk) = {
  709. .name = "generic-clk",
  710. .id = UCLASS_CLK,
  711. .probe = at91_clk_probe,
  712. .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
  713. .priv_auto = sizeof(struct generic_clk_priv),
  714. .plat_auto = sizeof(struct pmc_platdata),
  715. .ops = &generic_clk_ops,
  716. };
  717. #endif /* CONFIG_AT91_GENERIC_CLK */
  718. /* USB clock specific code. */
  719. #ifdef CONFIG_AT91_USB_CLK
  720. #define AT91_USB_CLK_SOURCE_MAX 2
  721. #define AT91_USB_CLK_MAX_DIV 15
  722. struct at91_usb_clk_priv {
  723. u32 num_clksource;
  724. };
  725. static ulong at91_usb_clk_get_rate(struct clk *clk)
  726. {
  727. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  728. struct at91_pmc *pmc = plat->reg_base;
  729. struct clk source;
  730. u32 tmp, usbdiv;
  731. u8 source_index;
  732. int ret;
  733. tmp = readl(&pmc->pcr);
  734. source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
  735. AT91_PMC_USB_USBS_MASK;
  736. usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
  737. ret = clk_get_by_index(clk->dev, source_index, &source);
  738. if (ret)
  739. return 0;
  740. return clk_get_rate(&source) / (usbdiv + 1);
  741. }
  742. static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
  743. {
  744. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  745. struct at91_pmc *pmc = plat->reg_base;
  746. struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
  747. struct clk source, best_source;
  748. ulong tmp_rate, best_rate = rate, source_rate;
  749. int tmp_diff, best_diff = -1;
  750. u32 div, best_div = 0;
  751. u8 best_source_index = 0;
  752. u8 i;
  753. u32 tmp;
  754. int ret;
  755. for (i = 0; i < priv->num_clksource; i++) {
  756. ret = clk_get_by_index(clk->dev, i, &source);
  757. if (ret)
  758. return ret;
  759. source_rate = clk_get_rate(&source);
  760. if (IS_ERR_VALUE(source_rate))
  761. return source_rate;
  762. for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
  763. tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
  764. tmp_diff = abs(rate - tmp_rate);
  765. if (best_diff < 0 || best_diff > tmp_diff) {
  766. best_rate = tmp_rate;
  767. best_diff = tmp_diff;
  768. best_div = div - 1;
  769. best_source = source;
  770. best_source_index = i;
  771. }
  772. if (!best_diff || tmp_rate < rate)
  773. break;
  774. }
  775. if (!best_diff)
  776. break;
  777. }
  778. debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
  779. best_source.dev->name, best_rate, best_div);
  780. ret = clk_enable(&best_source);
  781. if (ret)
  782. return ret;
  783. tmp = AT91_PMC_USB_USBS_(best_source_index) |
  784. AT91_PMC_USB_DIV_(best_div);
  785. writel(tmp, &pmc->usb);
  786. return 0;
  787. }
  788. static struct clk_ops at91_usb_clk_ops = {
  789. .get_rate = at91_usb_clk_get_rate,
  790. .set_rate = at91_usb_clk_set_rate,
  791. };
  792. static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
  793. {
  794. struct at91_usb_clk_priv *priv = dev_get_priv(dev);
  795. u32 cells[AT91_USB_CLK_SOURCE_MAX];
  796. u32 num_clksource;
  797. num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
  798. dev_of_offset(dev),
  799. "clocks", cells,
  800. AT91_USB_CLK_SOURCE_MAX);
  801. if (!num_clksource)
  802. return -1;
  803. priv->num_clksource = num_clksource;
  804. return 0;
  805. }
  806. static int at91_usb_clk_probe(struct udevice *dev)
  807. {
  808. return at91_pmc_core_probe(dev);
  809. }
  810. static const struct udevice_id at91_usb_clk_match[] = {
  811. { .compatible = "atmel,at91sam9x5-clk-usb" },
  812. {}
  813. };
  814. U_BOOT_DRIVER(at91_usb_clk) = {
  815. .name = "at91-usb-clk",
  816. .id = UCLASS_CLK,
  817. .of_match = at91_usb_clk_match,
  818. .probe = at91_usb_clk_probe,
  819. .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
  820. .priv_auto = sizeof(struct at91_usb_clk_priv),
  821. .plat_auto = sizeof(struct pmc_platdata),
  822. .ops = &at91_usb_clk_ops,
  823. };
  824. #endif /* CONFIG_AT91_USB_CLK */