clk-agilex.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dm/lists.h>
  11. #include <dm/util.h>
  12. #include <dt-bindings/clock/agilex-clock.h>
  13. #include <linux/bitops.h>
  14. #include <asm/arch/clock_manager.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct socfpga_clk_platdata {
  17. void __iomem *regs;
  18. };
  19. /*
  20. * function to write the bypass register which requires a poll of the
  21. * busy bit
  22. */
  23. static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
  24. {
  25. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
  26. cm_wait_for_fsm();
  27. }
  28. static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
  29. {
  30. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
  31. cm_wait_for_fsm();
  32. }
  33. /* function to write the ctrl register which requires a poll of the busy bit */
  34. static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
  35. {
  36. CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
  37. cm_wait_for_fsm();
  38. }
  39. #define MEMBUS_MAINPLL 0
  40. #define MEMBUS_PERPLL 1
  41. #define MEMBUS_TIMEOUT 1000
  42. #define MEMBUS_CLKSLICE_REG 0x27
  43. #define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3
  44. #define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6
  45. #define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03
  46. #define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07
  47. static const struct {
  48. u32 reg;
  49. u32 val;
  50. u32 mask;
  51. } membus_pll[] = {
  52. {
  53. MEMBUS_CLKSLICE_REG,
  54. /*
  55. * BIT[7:7]
  56. * Enable source synchronous mode
  57. */
  58. BIT(7),
  59. BIT(7)
  60. },
  61. {
  62. MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
  63. /*
  64. * BIT[0:0]
  65. * Sets synthcalfosc_init_centerfreq=1 to limit overshoot
  66. * frequency during lock
  67. */
  68. BIT(0),
  69. BIT(0)
  70. },
  71. {
  72. MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG,
  73. /*
  74. * BIT[0:0]
  75. * Sets synthppm_watchdogtmr_vf0=1 to give the pll more time
  76. * to settle before lock is asserted.
  77. */
  78. BIT(0),
  79. BIT(0)
  80. },
  81. {
  82. MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG,
  83. /*
  84. * BIT[6:0]
  85. * Centering duty cycle for clkslice0 output
  86. */
  87. 0x4a,
  88. GENMASK(6, 0)
  89. },
  90. {
  91. MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG,
  92. /*
  93. * BIT[6:0]
  94. * Centering duty cycle for clkslice1 output
  95. */
  96. 0x4a,
  97. GENMASK(6, 0)
  98. },
  99. };
  100. static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
  101. int timeout)
  102. {
  103. int cnt = 0;
  104. u32 req_status;
  105. if (pll == MEMBUS_MAINPLL)
  106. req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
  107. else
  108. req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
  109. while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
  110. if (pll == MEMBUS_MAINPLL)
  111. req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
  112. else
  113. req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
  114. cnt++;
  115. }
  116. if (cnt >= timeout)
  117. return -ETIMEDOUT;
  118. return 0;
  119. }
  120. static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
  121. u32 addr_offset, u32 wdat, int timeout)
  122. {
  123. u32 addr;
  124. u32 val;
  125. addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
  126. val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
  127. (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
  128. if (pll == MEMBUS_MAINPLL)
  129. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
  130. else
  131. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
  132. debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
  133. return membus_wait_for_req(plat, pll, timeout);
  134. }
  135. static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
  136. u32 addr_offset, u32 *rdata, int timeout)
  137. {
  138. u32 addr;
  139. u32 val;
  140. addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
  141. val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
  142. if (pll == MEMBUS_MAINPLL)
  143. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
  144. else
  145. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
  146. *rdata = 0;
  147. if (membus_wait_for_req(plat, pll, timeout))
  148. return -ETIMEDOUT;
  149. if (pll == MEMBUS_MAINPLL)
  150. *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
  151. else
  152. *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
  153. debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
  154. return 0;
  155. }
  156. static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll)
  157. {
  158. int i;
  159. u32 rdata;
  160. for (i = 0; i < ARRAY_SIZE(membus_pll); i++) {
  161. membus_read_pll(plat, pll, membus_pll[i].reg,
  162. &rdata, MEMBUS_TIMEOUT);
  163. membus_write_pll(plat, pll, membus_pll[i].reg,
  164. ((rdata & ~membus_pll[i].mask) | membus_pll[i].val),
  165. MEMBUS_TIMEOUT);
  166. }
  167. }
  168. static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
  169. {
  170. u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
  171. mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
  172. arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
  173. CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
  174. drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
  175. CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
  176. refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
  177. CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
  178. mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
  179. if (!mscnt)
  180. mscnt = 1;
  181. hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
  182. CLKMGR_VCOCALIB_HSCNT_CONST;
  183. vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
  184. ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
  185. CLKMGR_VCOCALIB_MSCNT_MASK);
  186. /* Dump all the pll calibration settings for debug purposes */
  187. debug("mdiv : %d\n", mdiv);
  188. debug("arefclkdiv : %d\n", arefclkdiv);
  189. debug("drefclkdiv : %d\n", drefclkdiv);
  190. debug("refclkdiv : %d\n", refclkdiv);
  191. debug("mscnt : %d\n", mscnt);
  192. debug("hscnt : %d\n", hscnt);
  193. debug("vcocalib : 0x%08x\n", vcocalib);
  194. return vcocalib;
  195. }
  196. /*
  197. * Setup clocks while making no assumptions about previous state of the clocks.
  198. */
  199. static void clk_basic_init(struct udevice *dev,
  200. const struct cm_config * const cfg)
  201. {
  202. struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
  203. u32 vcocalib;
  204. if (!cfg)
  205. return;
  206. #ifdef CONFIG_SPL_BUILD
  207. /* Always force clock manager into boot mode before any configuration */
  208. clk_write_ctrl(plat,
  209. CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
  210. #else
  211. /* Skip clock configuration in SSBL if it's not in boot mode */
  212. if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
  213. return;
  214. #endif
  215. /* Put both PLLs in bypass */
  216. clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
  217. clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
  218. /* Put both PLLs in Reset and Power Down */
  219. CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
  220. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  221. CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
  222. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  223. /* setup main PLL dividers where calculate the vcocalib value */
  224. vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
  225. CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
  226. CLKMGR_MAINPLL_PLLGLOB);
  227. CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
  228. CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
  229. CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
  230. CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
  231. CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
  232. CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
  233. CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
  234. CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
  235. CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
  236. CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
  237. /* setup peripheral PLL dividers where calculate the vcocalib value */
  238. vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
  239. CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
  240. CLKMGR_PERPLL_PLLGLOB);
  241. CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
  242. CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
  243. CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
  244. CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
  245. CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
  246. CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
  247. CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
  248. CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
  249. CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
  250. /* Take both PLL out of reset and power up */
  251. CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
  252. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  253. CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
  254. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  255. /* Membus programming for mainpll */
  256. membus_pll_configs(plat, MEMBUS_MAINPLL);
  257. /* Membus programming for peripll */
  258. membus_pll_configs(plat, MEMBUS_PERPLL);
  259. cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
  260. /* Configure ping pong counters in altera group */
  261. CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
  262. CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
  263. CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
  264. CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
  265. CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
  266. CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
  267. CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
  268. CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
  269. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
  270. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
  271. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
  272. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  273. CLKMGR_MAINPLL_PLLGLOB);
  274. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
  275. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  276. CLKMGR_PERPLL_PLLGLOB);
  277. /* Take all PLLs out of bypass */
  278. clk_write_bypass_mainpll(plat, 0);
  279. clk_write_bypass_perpll(plat, 0);
  280. /* Clear the loss of lock bits (write 1 to clear) */
  281. CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
  282. CLKMGR_INTER_PERPLLLOST_MASK |
  283. CLKMGR_INTER_MAINPLLLOST_MASK);
  284. /* Take all ping pong counters out of reset */
  285. CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
  286. CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
  287. /* Out of boot mode */
  288. clk_write_ctrl(plat,
  289. CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
  290. }
  291. static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
  292. u32 pllglob_reg, u32 pllm_reg)
  293. {
  294. u64 fref, arefdiv, mdiv, reg, vco;
  295. reg = CM_REG_READL(plat, pllglob_reg);
  296. fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
  297. CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
  298. switch (fref) {
  299. case CLKMGR_VCO_PSRC_EOSC1:
  300. fref = cm_get_osc_clk_hz();
  301. break;
  302. case CLKMGR_VCO_PSRC_INTOSC:
  303. fref = cm_get_intosc_clk_hz();
  304. break;
  305. case CLKMGR_VCO_PSRC_F2S:
  306. fref = cm_get_fpga_clk_hz();
  307. break;
  308. }
  309. arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
  310. CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
  311. mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
  312. vco = fref / arefdiv;
  313. vco = vco * mdiv;
  314. return vco;
  315. }
  316. static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
  317. {
  318. return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
  319. CLKMGR_MAINPLL_PLLM);
  320. }
  321. static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
  322. {
  323. return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
  324. CLKMGR_PERPLL_PLLM);
  325. }
  326. static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
  327. {
  328. u32 clksrc = CM_REG_READL(plat, reg);
  329. return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
  330. }
  331. static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
  332. u32 main_reg, u32 per_reg)
  333. {
  334. u64 clock;
  335. u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
  336. switch (clklsrc) {
  337. case CLKMGR_CLKSRC_MAIN:
  338. clock = clk_get_main_vco_clk_hz(plat);
  339. clock /= (CM_REG_READL(plat, main_reg) &
  340. CLKMGR_CLKCNT_MSK);
  341. break;
  342. case CLKMGR_CLKSRC_PER:
  343. clock = clk_get_per_vco_clk_hz(plat);
  344. clock /= (CM_REG_READL(plat, per_reg) &
  345. CLKMGR_CLKCNT_MSK);
  346. break;
  347. case CLKMGR_CLKSRC_OSC1:
  348. clock = cm_get_osc_clk_hz();
  349. break;
  350. case CLKMGR_CLKSRC_INTOSC:
  351. clock = cm_get_intosc_clk_hz();
  352. break;
  353. case CLKMGR_CLKSRC_FPGA:
  354. clock = cm_get_fpga_clk_hz();
  355. break;
  356. default:
  357. return 0;
  358. }
  359. return clock;
  360. }
  361. static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
  362. {
  363. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
  364. CLKMGR_MAINPLL_PLLC0,
  365. CLKMGR_PERPLL_PLLC0);
  366. clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
  367. CLKMGR_CLKCNT_MSK);
  368. return clock;
  369. }
  370. static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
  371. {
  372. return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
  373. CLKMGR_MAINPLL_PLLC1,
  374. CLKMGR_PERPLL_PLLC1);
  375. }
  376. static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
  377. {
  378. u64 clock = clk_get_l3_main_clk_hz(plat);
  379. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  380. CLKMGR_NOCDIV_L4MAIN_OFFSET) &
  381. CLKMGR_NOCDIV_DIVIDER_MASK);
  382. return clock;
  383. }
  384. static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
  385. {
  386. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
  387. CLKMGR_MAINPLL_PLLC3,
  388. CLKMGR_PERPLL_PLLC3);
  389. clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
  390. CLKMGR_CLKCNT_MSK);
  391. return clock / 4;
  392. }
  393. static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
  394. {
  395. u64 clock = clk_get_l3_main_clk_hz(plat);
  396. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  397. CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
  398. CLKMGR_NOCDIV_DIVIDER_MASK);
  399. return clock;
  400. }
  401. static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
  402. {
  403. u64 clock = clk_get_l3_main_clk_hz(plat);
  404. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  405. CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
  406. CLKMGR_NOCDIV_DIVIDER_MASK);
  407. return clock;
  408. }
  409. static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
  410. {
  411. if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
  412. return clk_get_l3_main_clk_hz(plat) / 2;
  413. return clk_get_l3_main_clk_hz(plat) / 4;
  414. }
  415. static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
  416. {
  417. bool emacsel_a;
  418. u32 ctl;
  419. u32 ctr_reg;
  420. u32 clock;
  421. u32 div;
  422. u32 reg;
  423. /* Get EMAC clock source */
  424. ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
  425. if (emac_id == AGILEX_EMAC0_CLK)
  426. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
  427. CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
  428. else if (emac_id == AGILEX_EMAC1_CLK)
  429. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
  430. CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
  431. else if (emac_id == AGILEX_EMAC2_CLK)
  432. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
  433. CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
  434. else
  435. return 0;
  436. if (ctl) {
  437. /* EMAC B source */
  438. emacsel_a = false;
  439. ctr_reg = CLKMGR_ALTR_EMACBCTR;
  440. } else {
  441. /* EMAC A source */
  442. emacsel_a = true;
  443. ctr_reg = CLKMGR_ALTR_EMACACTR;
  444. }
  445. reg = CM_REG_READL(plat, ctr_reg);
  446. clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
  447. >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
  448. div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
  449. >> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
  450. switch (clock) {
  451. case CLKMGR_CLKSRC_MAIN:
  452. clock = clk_get_main_vco_clk_hz(plat);
  453. if (emacsel_a) {
  454. clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
  455. CLKMGR_CLKCNT_MSK);
  456. } else {
  457. clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
  458. CLKMGR_CLKCNT_MSK);
  459. }
  460. break;
  461. case CLKMGR_CLKSRC_PER:
  462. clock = clk_get_per_vco_clk_hz(plat);
  463. if (emacsel_a) {
  464. clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
  465. CLKMGR_CLKCNT_MSK);
  466. } else {
  467. clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
  468. CLKMGR_CLKCNT_MSK);
  469. }
  470. break;
  471. case CLKMGR_CLKSRC_OSC1:
  472. clock = cm_get_osc_clk_hz();
  473. break;
  474. case CLKMGR_CLKSRC_INTOSC:
  475. clock = cm_get_intosc_clk_hz();
  476. break;
  477. case CLKMGR_CLKSRC_FPGA:
  478. clock = cm_get_fpga_clk_hz();
  479. break;
  480. }
  481. clock /= 1 + div;
  482. return clock;
  483. }
  484. static ulong socfpga_clk_get_rate(struct clk *clk)
  485. {
  486. struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
  487. switch (clk->id) {
  488. case AGILEX_MPU_CLK:
  489. return clk_get_mpu_clk_hz(plat);
  490. case AGILEX_L4_MAIN_CLK:
  491. return clk_get_l4_main_clk_hz(plat);
  492. case AGILEX_L4_SYS_FREE_CLK:
  493. return clk_get_l4_sys_free_clk_hz(plat);
  494. case AGILEX_L4_MP_CLK:
  495. return clk_get_l4_mp_clk_hz(plat);
  496. case AGILEX_L4_SP_CLK:
  497. return clk_get_l4_sp_clk_hz(plat);
  498. case AGILEX_SDMMC_CLK:
  499. return clk_get_sdmmc_clk_hz(plat);
  500. case AGILEX_EMAC0_CLK:
  501. case AGILEX_EMAC1_CLK:
  502. case AGILEX_EMAC2_CLK:
  503. return clk_get_emac_clk_hz(plat, clk->id);
  504. case AGILEX_USB_CLK:
  505. case AGILEX_NAND_X_CLK:
  506. return clk_get_l4_mp_clk_hz(plat);
  507. case AGILEX_NAND_CLK:
  508. return clk_get_l4_mp_clk_hz(plat) / 4;
  509. default:
  510. return -ENXIO;
  511. }
  512. }
  513. static int socfpga_clk_enable(struct clk *clk)
  514. {
  515. return 0;
  516. }
  517. static int socfpga_clk_probe(struct udevice *dev)
  518. {
  519. const struct cm_config *cm_default_cfg = cm_get_default_config();
  520. clk_basic_init(dev, cm_default_cfg);
  521. return 0;
  522. }
  523. static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
  524. {
  525. struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
  526. fdt_addr_t addr;
  527. addr = dev_read_addr(dev);
  528. if (addr == FDT_ADDR_T_NONE)
  529. return -EINVAL;
  530. plat->regs = (void __iomem *)addr;
  531. return 0;
  532. }
  533. static struct clk_ops socfpga_clk_ops = {
  534. .enable = socfpga_clk_enable,
  535. .get_rate = socfpga_clk_get_rate,
  536. };
  537. static const struct udevice_id socfpga_clk_match[] = {
  538. { .compatible = "intel,agilex-clkmgr" },
  539. {}
  540. };
  541. U_BOOT_DRIVER(socfpga_agilex_clk) = {
  542. .name = "clk-agilex",
  543. .id = UCLASS_CLK,
  544. .of_match = socfpga_clk_match,
  545. .ops = &socfpga_clk_ops,
  546. .probe = socfpga_clk_probe,
  547. .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
  548. .plat_auto = sizeof(struct socfpga_clk_platdata),
  549. };