stm32-adc.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
  5. *
  6. * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
  7. */
  8. #include <common.h>
  9. #include <adc.h>
  10. #include <dm.h>
  11. #include <asm/io.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/iopoll.h>
  16. #include "stm32-adc-core.h"
  17. /* STM32H7 - Registers for each ADC instance */
  18. #define STM32H7_ADC_ISR 0x00
  19. #define STM32H7_ADC_CR 0x08
  20. #define STM32H7_ADC_CFGR 0x0C
  21. #define STM32H7_ADC_SMPR1 0x14
  22. #define STM32H7_ADC_SMPR2 0x18
  23. #define STM32H7_ADC_PCSEL 0x1C
  24. #define STM32H7_ADC_SQR1 0x30
  25. #define STM32H7_ADC_DR 0x40
  26. #define STM32H7_ADC_DIFSEL 0xC0
  27. /* STM32H7_ADC_ISR - bit fields */
  28. #define STM32MP1_VREGREADY BIT(12)
  29. #define STM32H7_EOC BIT(2)
  30. #define STM32H7_ADRDY BIT(0)
  31. /* STM32H7_ADC_CR - bit fields */
  32. #define STM32H7_DEEPPWD BIT(29)
  33. #define STM32H7_ADVREGEN BIT(28)
  34. #define STM32H7_BOOST BIT(8)
  35. #define STM32H7_ADSTART BIT(2)
  36. #define STM32H7_ADDIS BIT(1)
  37. #define STM32H7_ADEN BIT(0)
  38. /* STM32H7_ADC_CFGR bit fields */
  39. #define STM32H7_EXTEN GENMASK(11, 10)
  40. #define STM32H7_DMNGT GENMASK(1, 0)
  41. /* STM32H7_ADC_SQR1 - bit fields */
  42. #define STM32H7_SQ1_SHIFT 6
  43. /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
  44. #define STM32H7_BOOST_CLKRATE 20000000UL
  45. #define STM32_ADC_CH_MAX 20 /* max number of channels */
  46. #define STM32_ADC_TIMEOUT_US 100000
  47. struct stm32_adc_cfg {
  48. unsigned int max_channels;
  49. unsigned int num_bits;
  50. bool has_vregready;
  51. };
  52. struct stm32_adc {
  53. void __iomem *regs;
  54. int active_channel;
  55. const struct stm32_adc_cfg *cfg;
  56. };
  57. static int stm32_adc_stop(struct udevice *dev)
  58. {
  59. struct stm32_adc *adc = dev_get_priv(dev);
  60. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);
  61. clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
  62. /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
  63. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
  64. adc->active_channel = -1;
  65. return 0;
  66. }
  67. static int stm32_adc_start_channel(struct udevice *dev, int channel)
  68. {
  69. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  70. struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
  71. struct stm32_adc *adc = dev_get_priv(dev);
  72. int ret;
  73. u32 val;
  74. /* Exit deep power down, then enable ADC voltage regulator */
  75. clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
  76. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
  77. if (common->rate > STM32H7_BOOST_CLKRATE)
  78. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
  79. /* Wait for startup time */
  80. if (!adc->cfg->has_vregready) {
  81. udelay(20);
  82. } else {
  83. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  84. val & STM32MP1_VREGREADY,
  85. STM32_ADC_TIMEOUT_US);
  86. if (ret < 0) {
  87. stm32_adc_stop(dev);
  88. dev_err(dev, "Failed to enable vreg: %d\n", ret);
  89. return ret;
  90. }
  91. }
  92. /* Only use single ended channels */
  93. writel(0, adc->regs + STM32H7_ADC_DIFSEL);
  94. /* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
  95. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
  96. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  97. val & STM32H7_ADRDY, STM32_ADC_TIMEOUT_US);
  98. if (ret < 0) {
  99. stm32_adc_stop(dev);
  100. dev_err(dev, "Failed to enable ADC: %d\n", ret);
  101. return ret;
  102. }
  103. /* Preselect channels */
  104. writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
  105. /* Set sampling time to max value by default */
  106. writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
  107. writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);
  108. /* Program regular sequence: chan in SQ1 & len = 0 for one channel */
  109. writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
  110. /* Trigger detection disabled (conversion can be launched in SW) */
  111. clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
  112. STM32H7_DMNGT);
  113. adc->active_channel = channel;
  114. return 0;
  115. }
  116. static int stm32_adc_channel_data(struct udevice *dev, int channel,
  117. unsigned int *data)
  118. {
  119. struct stm32_adc *adc = dev_get_priv(dev);
  120. int ret;
  121. u32 val;
  122. if (channel != adc->active_channel) {
  123. dev_err(dev, "Requested channel is not active!\n");
  124. return -EINVAL;
  125. }
  126. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);
  127. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  128. val & STM32H7_EOC, STM32_ADC_TIMEOUT_US);
  129. if (ret < 0) {
  130. dev_err(dev, "conversion timed out: %d\n", ret);
  131. return ret;
  132. }
  133. *data = readl(adc->regs + STM32H7_ADC_DR);
  134. return 0;
  135. }
  136. static int stm32_adc_chan_of_init(struct udevice *dev)
  137. {
  138. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  139. struct stm32_adc *adc = dev_get_priv(dev);
  140. u32 chans[STM32_ADC_CH_MAX];
  141. unsigned int i, num_channels;
  142. int ret;
  143. /* Retrieve single ended channels listed in device tree */
  144. ret = dev_read_size(dev, "st,adc-channels");
  145. if (ret < 0) {
  146. dev_err(dev, "can't get st,adc-channels: %d\n", ret);
  147. return ret;
  148. }
  149. num_channels = ret / sizeof(u32);
  150. if (num_channels > adc->cfg->max_channels) {
  151. dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
  152. return -EINVAL;
  153. }
  154. ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
  155. if (ret < 0) {
  156. dev_err(dev, "can't read st,adc-channels: %d\n", ret);
  157. return ret;
  158. }
  159. for (i = 0; i < num_channels; i++) {
  160. if (chans[i] >= adc->cfg->max_channels) {
  161. dev_err(dev, "bad channel %u\n", chans[i]);
  162. return -EINVAL;
  163. }
  164. uc_pdata->channel_mask |= 1 << chans[i];
  165. }
  166. uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
  167. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  168. uc_pdata->data_timeout_us = 100000;
  169. return 0;
  170. }
  171. static int stm32_adc_probe(struct udevice *dev)
  172. {
  173. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  174. struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
  175. struct stm32_adc *adc = dev_get_priv(dev);
  176. int offset;
  177. offset = dev_read_u32_default(dev, "reg", -ENODATA);
  178. if (offset < 0) {
  179. dev_err(dev, "Can't read reg property\n");
  180. return offset;
  181. }
  182. adc->regs = common->base + offset;
  183. adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);
  184. /* VDD supplied by common vref pin */
  185. uc_pdata->vdd_supply = common->vref;
  186. uc_pdata->vdd_microvolts = common->vref_uv;
  187. uc_pdata->vss_microvolts = 0;
  188. return stm32_adc_chan_of_init(dev);
  189. }
  190. static const struct adc_ops stm32_adc_ops = {
  191. .start_channel = stm32_adc_start_channel,
  192. .channel_data = stm32_adc_channel_data,
  193. .stop = stm32_adc_stop,
  194. };
  195. static const struct stm32_adc_cfg stm32h7_adc_cfg = {
  196. .num_bits = 16,
  197. .max_channels = STM32_ADC_CH_MAX,
  198. };
  199. static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
  200. .num_bits = 16,
  201. .max_channels = STM32_ADC_CH_MAX,
  202. .has_vregready = true,
  203. };
  204. static const struct udevice_id stm32_adc_ids[] = {
  205. { .compatible = "st,stm32h7-adc",
  206. .data = (ulong)&stm32h7_adc_cfg },
  207. { .compatible = "st,stm32mp1-adc",
  208. .data = (ulong)&stm32mp1_adc_cfg },
  209. {}
  210. };
  211. U_BOOT_DRIVER(stm32_adc) = {
  212. .name = "stm32-adc",
  213. .id = UCLASS_ADC,
  214. .of_match = stm32_adc_ids,
  215. .probe = stm32_adc_probe,
  216. .ops = &stm32_adc_ops,
  217. .priv_auto = sizeof(struct stm32_adc),
  218. };