rockchip-saradc.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017, Fuzhou Rockchip Electronics Co., Ltd
  4. *
  5. * Rockchip SARADC driver for U-Boot
  6. */
  7. #include <common.h>
  8. #include <adc.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/err.h>
  15. #define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
  16. #define SARADC_CTRL_POWER_CTRL BIT(3)
  17. #define SARADC_CTRL_IRQ_ENABLE BIT(5)
  18. #define SARADC_CTRL_IRQ_STATUS BIT(6)
  19. #define SARADC_TIMEOUT (100 * 1000)
  20. struct rockchip_saradc_regs {
  21. unsigned int data;
  22. unsigned int stas;
  23. unsigned int ctrl;
  24. unsigned int dly_pu_soc;
  25. };
  26. struct rockchip_saradc_data {
  27. int num_bits;
  28. int num_channels;
  29. unsigned long clk_rate;
  30. };
  31. struct rockchip_saradc_priv {
  32. struct rockchip_saradc_regs *regs;
  33. int active_channel;
  34. const struct rockchip_saradc_data *data;
  35. };
  36. int rockchip_saradc_channel_data(struct udevice *dev, int channel,
  37. unsigned int *data)
  38. {
  39. struct rockchip_saradc_priv *priv = dev_get_priv(dev);
  40. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  41. if (channel != priv->active_channel) {
  42. pr_err("Requested channel is not active!");
  43. return -EINVAL;
  44. }
  45. if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) !=
  46. SARADC_CTRL_IRQ_STATUS)
  47. return -EBUSY;
  48. /* Read value */
  49. *data = readl(&priv->regs->data);
  50. *data &= uc_pdata->data_mask;
  51. /* Power down adc */
  52. writel(0, &priv->regs->ctrl);
  53. return 0;
  54. }
  55. int rockchip_saradc_start_channel(struct udevice *dev, int channel)
  56. {
  57. struct rockchip_saradc_priv *priv = dev_get_priv(dev);
  58. if (channel < 0 || channel >= priv->data->num_channels) {
  59. pr_err("Requested channel is invalid!");
  60. return -EINVAL;
  61. }
  62. /* 8 clock periods as delay between power up and start cmd */
  63. writel(8, &priv->regs->dly_pu_soc);
  64. /* Select the channel to be used and trigger conversion */
  65. writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) |
  66. SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl);
  67. priv->active_channel = channel;
  68. return 0;
  69. }
  70. int rockchip_saradc_stop(struct udevice *dev)
  71. {
  72. struct rockchip_saradc_priv *priv = dev_get_priv(dev);
  73. /* Power down adc */
  74. writel(0, &priv->regs->ctrl);
  75. priv->active_channel = -1;
  76. return 0;
  77. }
  78. int rockchip_saradc_probe(struct udevice *dev)
  79. {
  80. struct rockchip_saradc_priv *priv = dev_get_priv(dev);
  81. struct clk clk;
  82. int ret;
  83. ret = clk_get_by_index(dev, 0, &clk);
  84. if (ret)
  85. return ret;
  86. ret = clk_set_rate(&clk, priv->data->clk_rate);
  87. if (IS_ERR_VALUE(ret))
  88. return ret;
  89. priv->active_channel = -1;
  90. return 0;
  91. }
  92. int rockchip_saradc_ofdata_to_platdata(struct udevice *dev)
  93. {
  94. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  95. struct rockchip_saradc_priv *priv = dev_get_priv(dev);
  96. struct rockchip_saradc_data *data;
  97. data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
  98. priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev);
  99. if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) {
  100. pr_err("Dev: %s - can't get address!", dev->name);
  101. return -ENODATA;
  102. }
  103. priv->data = data;
  104. uc_pdata->data_mask = (1 << priv->data->num_bits) - 1;;
  105. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  106. uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5;
  107. uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
  108. return 0;
  109. }
  110. static const struct adc_ops rockchip_saradc_ops = {
  111. .start_channel = rockchip_saradc_start_channel,
  112. .channel_data = rockchip_saradc_channel_data,
  113. .stop = rockchip_saradc_stop,
  114. };
  115. static const struct rockchip_saradc_data saradc_data = {
  116. .num_bits = 10,
  117. .num_channels = 3,
  118. .clk_rate = 1000000,
  119. };
  120. static const struct rockchip_saradc_data rk3066_tsadc_data = {
  121. .num_bits = 12,
  122. .num_channels = 2,
  123. .clk_rate = 50000,
  124. };
  125. static const struct rockchip_saradc_data rk3399_saradc_data = {
  126. .num_bits = 10,
  127. .num_channels = 6,
  128. .clk_rate = 1000000,
  129. };
  130. static const struct udevice_id rockchip_saradc_ids[] = {
  131. { .compatible = "rockchip,saradc",
  132. .data = (ulong)&saradc_data },
  133. { .compatible = "rockchip,rk3066-tsadc",
  134. .data = (ulong)&rk3066_tsadc_data },
  135. { .compatible = "rockchip,rk3399-saradc",
  136. .data = (ulong)&rk3399_saradc_data },
  137. { }
  138. };
  139. U_BOOT_DRIVER(rockchip_saradc) = {
  140. .name = "rockchip_saradc",
  141. .id = UCLASS_ADC,
  142. .of_match = rockchip_saradc_ids,
  143. .ops = &rockchip_saradc_ops,
  144. .probe = rockchip_saradc_probe,
  145. .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata,
  146. .priv_auto = sizeof(struct rockchip_saradc_priv),
  147. };