meson-saradc.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  4. * Copyright (C) 2018 BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
  8. */
  9. #include <common.h>
  10. #include <adc.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/math64.h>
  19. #include <linux/bitfield.h>
  20. #define MESON_SAR_ADC_REG0 0x00
  21. #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
  22. #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
  23. #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
  24. #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
  25. #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
  26. #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
  27. #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
  28. #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
  29. #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
  30. #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
  31. #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
  32. #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
  33. #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
  34. #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
  35. #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
  36. #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
  37. #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
  38. #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
  39. #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
  40. #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
  41. #define MESON_SAR_ADC_CHAN_LIST 0x04
  42. #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
  43. #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
  44. (GENMASK(2, 0) << ((_chan) * 3))
  45. #define MESON_SAR_ADC_AVG_CNTL 0x08
  46. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
  47. (16 + ((_chan) * 2))
  48. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
  49. (GENMASK(17, 16) << ((_chan) * 2))
  50. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  51. (0 + ((_chan) * 2))
  52. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
  53. (GENMASK(1, 0) << ((_chan) * 2))
  54. #define MESON_SAR_ADC_REG3 0x0c
  55. #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
  56. #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
  57. #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
  58. #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
  59. #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
  60. #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
  61. #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
  62. #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
  63. #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
  64. #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
  65. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
  66. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
  67. #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
  68. #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
  69. #define MESON_SAR_ADC_DELAY 0x10
  70. #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
  71. #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
  72. #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
  73. #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
  74. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
  75. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
  76. #define MESON_SAR_ADC_LAST_RD 0x14
  77. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
  78. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
  79. #define MESON_SAR_ADC_FIFO_RD 0x18
  80. #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
  81. #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
  82. #define MESON_SAR_ADC_AUX_SW 0x1c
  83. #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
  84. (8 + (((_chan) - 2) * 3))
  85. #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
  86. #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
  87. #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
  88. #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
  89. #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
  90. #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
  91. #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
  92. #define MESON_SAR_ADC_CHAN_10_SW 0x20
  93. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
  94. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
  95. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
  96. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
  97. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
  98. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
  99. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
  100. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
  101. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
  102. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
  103. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
  104. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
  105. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
  106. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
  107. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
  108. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
  109. #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
  110. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
  111. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
  112. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
  113. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
  114. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
  115. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
  116. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
  117. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
  118. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
  119. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
  120. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
  121. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
  122. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
  123. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
  124. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
  125. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
  126. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
  127. #define MESON_SAR_ADC_DELTA_10 0x28
  128. #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
  129. #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
  130. #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
  131. #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
  132. #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
  133. #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
  134. #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
  135. #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
  136. /*
  137. * NOTE: registers from here are undocumented (the vendor Linux kernel driver
  138. * and u-boot source served as reference). These only seem to be relevant on
  139. * GXBB and newer.
  140. */
  141. #define MESON_SAR_ADC_REG11 0x2c
  142. #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
  143. #define MESON_SAR_ADC_REG13 0x34
  144. #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
  145. #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
  146. #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
  147. #define NUM_CHANNELS 8
  148. #define MILLION 1000000
  149. struct meson_saradc_data {
  150. int num_bits;
  151. };
  152. struct meson_saradc_priv {
  153. const struct meson_saradc_data *data;
  154. struct regmap *regmap;
  155. struct clk core_clk;
  156. struct clk adc_clk;
  157. bool initialized;
  158. int active_channel;
  159. int calibbias;
  160. int calibscale;
  161. };
  162. static unsigned int
  163. meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
  164. {
  165. u32 regval;
  166. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  167. return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
  168. }
  169. static int meson_saradc_lock(struct meson_saradc_priv *priv)
  170. {
  171. uint val, timeout = 10000;
  172. /* prevent BL30 from using the SAR ADC while we are using it */
  173. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  174. MESON_SAR_ADC_DELAY_KERNEL_BUSY,
  175. MESON_SAR_ADC_DELAY_KERNEL_BUSY);
  176. /*
  177. * wait until BL30 releases it's lock (so we can use the SAR ADC)
  178. */
  179. do {
  180. udelay(1);
  181. regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
  182. } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
  183. if (timeout < 0) {
  184. printf("Timeout while waiting for BL30 unlock\n");
  185. return -ETIMEDOUT;
  186. }
  187. return 0;
  188. }
  189. static void meson_saradc_unlock(struct meson_saradc_priv *priv)
  190. {
  191. /* allow BL30 to use the SAR ADC again */
  192. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  193. MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
  194. }
  195. static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
  196. {
  197. unsigned int count, tmp;
  198. for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
  199. if (!meson_saradc_get_fifo_count(priv))
  200. break;
  201. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
  202. }
  203. }
  204. static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
  205. {
  206. int tmp;
  207. /* use val_calib = scale * val_raw + offset calibration function */
  208. tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
  209. return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
  210. }
  211. static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
  212. {
  213. uint regval, timeout = 10000;
  214. /*
  215. * NOTE: we need a small delay before reading the status, otherwise
  216. * the sample engine may not have started internally (which would
  217. * seem to us that sampling is already finished).
  218. */
  219. do {
  220. udelay(1);
  221. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  222. } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
  223. if (timeout < 0)
  224. return -ETIMEDOUT;
  225. return 0;
  226. }
  227. static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
  228. unsigned int channel, uint *val)
  229. {
  230. uint regval, fifo_chan, fifo_val, count;
  231. int ret;
  232. ret = meson_saradc_wait_busy_clear(priv);
  233. if (ret)
  234. return ret;
  235. count = meson_saradc_get_fifo_count(priv);
  236. if (count != 1) {
  237. printf("ADC FIFO has %d element(s) instead of one\n", count);
  238. return -EINVAL;
  239. }
  240. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
  241. fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
  242. if (fifo_chan != channel) {
  243. printf("ADC FIFO entry belongs to channel %d instead of %d\n",
  244. fifo_chan, channel);
  245. return -EINVAL;
  246. }
  247. fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
  248. fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
  249. *val = meson_saradc_calib_val(priv, fifo_val);
  250. return 0;
  251. }
  252. static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
  253. {
  254. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  255. MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
  256. MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
  257. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  258. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
  259. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
  260. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  261. MESON_SAR_ADC_REG0_SAMPLING_START,
  262. MESON_SAR_ADC_REG0_SAMPLING_START);
  263. }
  264. static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
  265. {
  266. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  267. MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
  268. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  269. MESON_SAR_ADC_REG0_SAMPLING_STOP,
  270. MESON_SAR_ADC_REG0_SAMPLING_STOP);
  271. /* wait until all modules are stopped */
  272. meson_saradc_wait_busy_clear(priv);
  273. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  274. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
  275. }
  276. enum meson_saradc_avg_mode {
  277. NO_AVERAGING = 0x0,
  278. MEAN_AVERAGING = 0x1,
  279. MEDIAN_AVERAGING = 0x2,
  280. };
  281. enum meson_saradc_num_samples {
  282. ONE_SAMPLE = 0x0,
  283. TWO_SAMPLES = 0x1,
  284. FOUR_SAMPLES = 0x2,
  285. EIGHT_SAMPLES = 0x3,
  286. };
  287. static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
  288. unsigned int channel,
  289. enum meson_saradc_avg_mode mode,
  290. enum meson_saradc_num_samples samples)
  291. {
  292. int val;
  293. val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
  294. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  295. MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
  296. val);
  297. val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
  298. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  299. MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
  300. }
  301. static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
  302. unsigned int channel)
  303. {
  304. uint regval;
  305. /*
  306. * the SAR ADC engine allows sampling multiple channels at the same
  307. * time. to keep it simple we're only working with one *internal*
  308. * channel, which starts counting at index 0 (which means: count = 1).
  309. */
  310. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
  311. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  312. MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
  313. /* map channel index 0 to the channel which we want to read */
  314. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
  315. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  316. MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
  317. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  318. channel);
  319. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  320. MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  321. regval);
  322. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  323. channel);
  324. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  325. MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  326. regval);
  327. if (channel == 6)
  328. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  329. MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
  330. }
  331. static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
  332. int chan, uint *val)
  333. {
  334. int ret;
  335. ret = meson_saradc_lock(priv);
  336. if (ret)
  337. return ret;
  338. /* clear the FIFO to make sure we're not reading old values */
  339. meson_saradc_clear_fifo(priv);
  340. meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
  341. meson_saradc_enable_channel(priv, chan);
  342. meson_saradc_start_sample_engine(priv);
  343. ret = meson_saradc_read_raw_sample(priv, chan, val);
  344. meson_saradc_stop_sample_engine(priv);
  345. meson_saradc_unlock(priv);
  346. if (ret) {
  347. printf("failed to read sample for channel %d: %d\n",
  348. chan, ret);
  349. return ret;
  350. }
  351. return 0;
  352. }
  353. static int meson_saradc_channel_data(struct udevice *dev, int channel,
  354. unsigned int *data)
  355. {
  356. struct meson_saradc_priv *priv = dev_get_priv(dev);
  357. if (channel != priv->active_channel) {
  358. pr_err("Requested channel is not active!");
  359. return -EINVAL;
  360. }
  361. return meson_saradc_get_sample(priv, channel, data);
  362. }
  363. enum meson_saradc_chan7_mux_sel {
  364. CHAN7_MUX_VSS = 0x0,
  365. CHAN7_MUX_VDD_DIV4 = 0x1,
  366. CHAN7_MUX_VDD_DIV2 = 0x2,
  367. CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
  368. CHAN7_MUX_VDD = 0x4,
  369. CHAN7_MUX_CH7_INPUT = 0x7,
  370. };
  371. static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
  372. enum meson_saradc_chan7_mux_sel sel)
  373. {
  374. u32 regval;
  375. regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
  376. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  377. MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
  378. udelay(20);
  379. }
  380. static int meson_saradc_calib(struct meson_saradc_priv *priv)
  381. {
  382. uint nominal0, nominal1, value0, value1;
  383. int ret;
  384. /* use points 25% and 75% for calibration */
  385. nominal0 = (1 << priv->data->num_bits) / 4;
  386. nominal1 = (1 << priv->data->num_bits) * 3 / 4;
  387. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
  388. udelay(20);
  389. ret = meson_saradc_get_sample(priv, 7, &value0);
  390. if (ret < 0)
  391. goto out;
  392. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
  393. udelay(20);
  394. ret = meson_saradc_get_sample(priv, 7, &value1);
  395. if (ret < 0)
  396. goto out;
  397. if (value1 <= value0) {
  398. ret = -EINVAL;
  399. goto out;
  400. }
  401. priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
  402. value1 - value0);
  403. priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
  404. MILLION);
  405. ret = 0;
  406. out:
  407. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  408. return ret;
  409. }
  410. static int meson_saradc_init(struct meson_saradc_priv *priv)
  411. {
  412. uint regval;
  413. int ret, i;
  414. priv->calibscale = MILLION;
  415. /*
  416. * make sure we start at CH7 input since the other muxes are only used
  417. * for internal calibration.
  418. */
  419. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  420. /*
  421. * leave sampling delay and the input clocks as configured by
  422. * BL30 to make sure BL30 gets the values it expects when
  423. * reading the temperature sensor.
  424. */
  425. regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
  426. if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
  427. return 0;
  428. meson_saradc_stop_sample_engine(priv);
  429. /* update the channel 6 MUX to select the temperature sensor */
  430. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  431. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
  432. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
  433. /* disable all channels by default */
  434. regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
  435. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  436. MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
  437. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  438. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
  439. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
  440. /* delay between two samples = (10+1) * 1uS */
  441. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  442. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  443. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
  444. 10));
  445. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  446. MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  447. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  448. 0));
  449. /* delay between two samples = (10+1) * 1uS */
  450. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  451. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  452. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  453. 10));
  454. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  455. MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  456. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  457. 1));
  458. /*
  459. * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
  460. * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
  461. */
  462. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
  463. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  464. MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
  465. regval);
  466. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
  467. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  468. MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
  469. regval);
  470. /*
  471. * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
  472. * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
  473. * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
  474. * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
  475. */
  476. regval = 0;
  477. for (i = 2; i <= 7; i++)
  478. regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
  479. regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
  480. regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
  481. regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
  482. ret = meson_saradc_lock(priv);
  483. if (ret)
  484. return ret;
  485. #if CONFIG_IS_ENABLED(CLK)
  486. ret = clk_enable(&priv->core_clk);
  487. if (ret)
  488. return ret;
  489. #endif
  490. regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
  491. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  492. MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
  493. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
  494. MESON_SAR_ADC_REG11_BANDGAP_EN,
  495. MESON_SAR_ADC_REG11_BANDGAP_EN);
  496. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  497. MESON_SAR_ADC_REG3_ADC_EN,
  498. MESON_SAR_ADC_REG3_ADC_EN);
  499. udelay(5);
  500. #if CONFIG_IS_ENABLED(CLK)
  501. ret = clk_enable(&priv->adc_clk);
  502. if (ret)
  503. return ret;
  504. #endif
  505. meson_saradc_unlock(priv);
  506. ret = meson_saradc_calib(priv);
  507. if (ret) {
  508. printf("calibration failed\n");
  509. return -EIO;
  510. }
  511. return 0;
  512. }
  513. static int meson_saradc_start_channel(struct udevice *dev, int channel)
  514. {
  515. struct meson_saradc_priv *priv = dev_get_priv(dev);
  516. if (channel < 0 || channel >= NUM_CHANNELS) {
  517. printf("Requested channel is invalid!");
  518. return -EINVAL;
  519. }
  520. if (!priv->initialized) {
  521. int ret;
  522. ret = meson_saradc_init(priv);
  523. if (ret)
  524. return ret;
  525. priv->initialized = true;
  526. }
  527. priv->active_channel = channel;
  528. return 0;
  529. }
  530. static int meson_saradc_stop(struct udevice *dev)
  531. {
  532. struct meson_saradc_priv *priv = dev_get_priv(dev);
  533. priv->active_channel = -1;
  534. return 0;
  535. }
  536. static int meson_saradc_probe(struct udevice *dev)
  537. {
  538. struct meson_saradc_priv *priv = dev_get_priv(dev);
  539. int ret;
  540. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  541. if (ret)
  542. return ret;
  543. #if CONFIG_IS_ENABLED(CLK)
  544. ret = clk_get_by_name(dev, "core", &priv->core_clk);
  545. if (ret)
  546. return ret;
  547. ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
  548. if (ret)
  549. return ret;
  550. #endif
  551. priv->active_channel = -1;
  552. return 0;
  553. }
  554. int meson_saradc_ofdata_to_platdata(struct udevice *dev)
  555. {
  556. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  557. struct meson_saradc_priv *priv = dev_get_priv(dev);
  558. priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
  559. uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
  560. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  561. uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
  562. uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
  563. return 0;
  564. }
  565. static const struct adc_ops meson_saradc_ops = {
  566. .start_channel = meson_saradc_start_channel,
  567. .channel_data = meson_saradc_channel_data,
  568. .stop = meson_saradc_stop,
  569. };
  570. static const struct meson_saradc_data gxbb_saradc_data = {
  571. .num_bits = 10,
  572. };
  573. static const struct meson_saradc_data gxl_saradc_data = {
  574. .num_bits = 12,
  575. };
  576. static const struct udevice_id meson_saradc_ids[] = {
  577. { .compatible = "amlogic,meson-gxbb-saradc",
  578. .data = (ulong)&gxbb_saradc_data },
  579. { .compatible = "amlogic,meson-gxl-saradc",
  580. .data = (ulong)&gxl_saradc_data },
  581. { .compatible = "amlogic,meson-gxm-saradc",
  582. .data = (ulong)&gxl_saradc_data },
  583. { }
  584. };
  585. U_BOOT_DRIVER(meson_saradc) = {
  586. .name = "meson_saradc",
  587. .id = UCLASS_ADC,
  588. .of_match = meson_saradc_ids,
  589. .ops = &meson_saradc_ops,
  590. .probe = meson_saradc_probe,
  591. .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
  592. .priv_auto = sizeof(struct meson_saradc_priv),
  593. };