amcore.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Sysam AMCORE (MCF5307 based) board
  4. *
  5. * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it>
  6. *
  7. * This file copies memory testdram() from sandburst/common/sb_common.c
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <asm/immap.h>
  12. #include <asm/io.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/serial_coldfire.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. void init_lcd(void)
  17. {
  18. /* setup for possible K0108 lcd connected on the parallel port */
  19. sim_t *sim = (sim_t *)(MMAP_SIM);
  20. out_be16(&sim->par, 0x300);
  21. gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  22. out_be16(&gpio->paddr, 0xfcff);
  23. out_be16(&gpio->padat, 0x0c00);
  24. }
  25. int checkboard(void)
  26. {
  27. puts("Board: ");
  28. puts("AMCORE v.001(alpha)\n");
  29. init_lcd();
  30. return 0;
  31. }
  32. /*
  33. * in dram_init we are here executing from flash
  34. * case 1:
  35. * is with no ACR/flash cache enabled
  36. * nop = 40ns (scope measured)
  37. */
  38. void fudelay(int usec)
  39. {
  40. while (usec--)
  41. asm volatile ("nop");
  42. }
  43. int dram_init(void)
  44. {
  45. u32 dramsize, RC;
  46. sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
  47. /*
  48. * SDRAM MT48LC4M32B2 details
  49. * Memory block 0: 16 MB of SDRAM at address $00000000
  50. * Port size: 32-bit port
  51. *
  52. * Memory block 0 wired as follows:
  53. * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
  54. * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
  55. *
  56. * Ensure that there is a delay of at least 100 microseconds from
  57. * processor reset to the following code so that the SDRAM is ready
  58. * for commands.
  59. */
  60. fudelay(100);
  61. /*
  62. * DCR
  63. * set proper RC as per specification
  64. */
  65. RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
  66. RC = (RC * 15) >> 4;
  67. /* 0x8000 is the faster option */
  68. out_be16(&dc->dcr, 0x8200 | RC);
  69. /*
  70. * DACR0, page mode continuous, CMD on A20 0x0300
  71. */
  72. out_be32(&dc->dacr0, 0x00003304);
  73. dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
  74. out_be32(&dc->dmr0, dramsize|1);
  75. /* issue a PRECHARGE ALL */
  76. out_be32(&dc->dacr0, 0x0000330c);
  77. out_be32((u32 *)0x00000004, 0xbeaddeed);
  78. /* issue AUTOREFRESH */
  79. out_be32(&dc->dacr0, 0x0000b304);
  80. /* let refresh occur */
  81. fudelay(1);
  82. out_be32(&dc->dacr0, 0x0000b344);
  83. out_be32((u32 *)0x00000c00, 0xbeaddeed);
  84. gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
  85. CONFIG_SYS_SDRAM_SIZE);
  86. return 0;
  87. }
  88. static struct coldfire_serial_platdata mcf5307_serial_plat = {
  89. .base = CONFIG_SYS_UART_BASE,
  90. .port = 0,
  91. .baudrate = CONFIG_BAUDRATE,
  92. };
  93. U_BOOT_DEVICE(coldfire_serial) = {
  94. .name = "serial_coldfire",
  95. .plat = &mcf5307_serial_plat,
  96. };