board.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Siemens CORVUS (AT91SAM9G45) based board
  4. * (C) Copyright 2013 Siemens AG
  5. *
  6. * Based on:
  7. * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
  8. * (C) Copyright 2007-2008
  9. * Stelian Pop <stelian@popies.net>
  10. * Lead Tech Design <www.leadtechdesign.com>
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <init.h>
  15. #include <log.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/at91sam9g45_matrix.h>
  18. #include <asm/arch/at91sam9_smc.h>
  19. #include <asm/arch/at91_common.h>
  20. #include <asm/arch/at91_rstc.h>
  21. #include <asm/arch/atmel_serial.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/clk.h>
  25. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  26. #include <net.h>
  27. #endif
  28. #ifndef CONFIG_DM_ETH
  29. #include <netdev.h>
  30. #endif
  31. #include <spi.h>
  32. #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  33. #include <asm/arch/atmel_usba_udc.h>
  34. #endif
  35. DECLARE_GLOBAL_DATA_PTR;
  36. static void corvus_request_gpio(void)
  37. {
  38. gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
  39. gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
  40. gpio_request(AT91_PIN_PD7, "d0");
  41. gpio_request(AT91_PIN_PD8, "d1");
  42. gpio_request(AT91_PIN_PA12, "d2");
  43. gpio_request(AT91_PIN_PA13, "d3");
  44. gpio_request(AT91_PIN_PA15, "d4");
  45. gpio_request(AT91_PIN_PB7, "recovery button");
  46. gpio_request(AT91_PIN_PD1, "USB0");
  47. gpio_request(AT91_PIN_PD3, "USB1");
  48. gpio_request(AT91_PIN_PB18, "SPICS1");
  49. gpio_request(AT91_PIN_PB3, "SPICS0");
  50. gpio_request(CONFIG_RED_LED, "red led");
  51. gpio_request(CONFIG_GREEN_LED, "green led");
  52. }
  53. static void corvus_nand_hw_init(void)
  54. {
  55. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  56. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  57. unsigned long csa;
  58. /* Enable CS3 */
  59. csa = readl(&matrix->ebicsa);
  60. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  61. writel(csa, &matrix->ebicsa);
  62. /* Configure SMC CS3 for NAND/SmartMedia */
  63. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  64. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  65. &smc->cs[3].setup);
  66. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  67. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  68. &smc->cs[3].pulse);
  69. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  70. &smc->cs[3].cycle);
  71. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  72. AT91_SMC_MODE_EXNW_DISABLE |
  73. #ifdef CONFIG_SYS_NAND_DBW_16
  74. AT91_SMC_MODE_DBW_16 |
  75. #else /* CONFIG_SYS_NAND_DBW_8 */
  76. AT91_SMC_MODE_DBW_8 |
  77. #endif
  78. AT91_SMC_MODE_TDF_CYCLE(3),
  79. &smc->cs[3].mode);
  80. at91_periph_clk_enable(ATMEL_ID_PIOC);
  81. at91_periph_clk_enable(ATMEL_ID_PIOA);
  82. /* Enable NandFlash */
  83. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  84. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  85. }
  86. #if defined(CONFIG_SPL_BUILD)
  87. #include <spl.h>
  88. #include <nand.h>
  89. void spl_board_init(void)
  90. {
  91. corvus_request_gpio();
  92. /*
  93. * For on the sam9m10g45ek board, the chip wm9711 stay in the test
  94. * mode, so it need do some action to exit mode.
  95. */
  96. at91_set_gpio_output(AT91_PIN_PD7, 0);
  97. at91_set_gpio_output(AT91_PIN_PD8, 0);
  98. at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
  99. at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
  100. at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
  101. at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
  102. at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
  103. corvus_nand_hw_init();
  104. /* Configure recovery button PINs */
  105. at91_set_gpio_input(AT91_PIN_PB7, 1);
  106. /* check if button is pressed */
  107. if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
  108. u32 boot_device;
  109. debug("Recovery button pressed\n");
  110. boot_device = spl_boot_device();
  111. switch (boot_device) {
  112. #ifdef CONFIG_SPL_NAND_SUPPORT
  113. case BOOT_DEVICE_NAND:
  114. nand_init();
  115. spl_nand_erase_one(0, 0);
  116. break;
  117. #endif
  118. }
  119. }
  120. }
  121. #include <asm/arch/atmel_mpddrc.h>
  122. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  123. {
  124. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  125. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  126. ATMEL_MPDDRC_CR_NR_ROW_14 |
  127. ATMEL_MPDDRC_CR_DIC_DS |
  128. ATMEL_MPDDRC_CR_DQMS_SHARED |
  129. ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
  130. ddr2->rtr = 0x24b;
  131. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
  132. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
  133. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
  134. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
  135. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
  136. 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
  137. 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
  138. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
  139. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
  140. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  141. 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  142. 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  143. ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  144. 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  145. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  146. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  147. }
  148. void mem_init(void)
  149. {
  150. struct atmel_mpddrc_config ddr2;
  151. ddr2_conf(&ddr2);
  152. at91_system_clk_enable(AT91_PMC_DDR);
  153. /* DDRAM2 Controller initialize */
  154. ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
  155. }
  156. #endif
  157. #ifdef CONFIG_CMD_USB
  158. static void taurus_usb_hw_init(void)
  159. {
  160. at91_periph_clk_enable(ATMEL_ID_PIODE);
  161. at91_set_gpio_output(AT91_PIN_PD1, 0);
  162. at91_set_gpio_output(AT91_PIN_PD3, 0);
  163. }
  164. #endif
  165. #ifdef CONFIG_MACB
  166. static void corvus_macb_hw_init(void)
  167. {
  168. /* Enable clock */
  169. at91_periph_clk_enable(ATMEL_ID_EMAC);
  170. /*
  171. * Disable pull-up on:
  172. * RXDV (PA15) => PHY normal mode (not Test mode)
  173. * ERX0 (PA12) => PHY ADDR0
  174. * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  175. *
  176. * PHY has internal pull-down
  177. */
  178. at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
  179. at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
  180. at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
  181. at91_phy_reset();
  182. /* Re-enable pull-up */
  183. at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
  184. at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
  185. at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
  186. /* And the pins. */
  187. at91_macb_hw_init();
  188. }
  189. #endif
  190. int board_early_init_f(void)
  191. {
  192. at91_seriald_hw_init();
  193. corvus_request_gpio();
  194. return 0;
  195. }
  196. #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  197. /* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */
  198. void at91_udp_hw_init(void)
  199. {
  200. /* Enable UPLL clock */
  201. at91_upll_clk_enable();
  202. /* Enable UDPHS clock */
  203. at91_periph_clk_enable(ATMEL_ID_UDPHS);
  204. }
  205. #endif
  206. int board_init(void)
  207. {
  208. /* address of boot parameters */
  209. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  210. /* we have to request the gpios again after relocation */
  211. corvus_request_gpio();
  212. #ifdef CONFIG_CMD_NAND
  213. corvus_nand_hw_init();
  214. #endif
  215. #ifdef CONFIG_ATMEL_SPI
  216. at91_spi0_hw_init(1 << 4);
  217. #endif
  218. #ifdef CONFIG_MACB
  219. corvus_macb_hw_init();
  220. #endif
  221. #ifdef CONFIG_CMD_USB
  222. taurus_usb_hw_init();
  223. #endif
  224. #ifdef CONFIG_USB_GADGET_ATMEL_USBA
  225. at91_udp_hw_init();
  226. usba_udc_probe(&pdata);
  227. #endif
  228. return 0;
  229. }
  230. int dram_init(void)
  231. {
  232. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  233. CONFIG_SYS_SDRAM_SIZE);
  234. return 0;
  235. }
  236. #ifndef CONFIG_DM_ETH
  237. int board_eth_init(struct bd_info *bis)
  238. {
  239. int rc = 0;
  240. #ifdef CONFIG_MACB
  241. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  242. #endif
  243. return rc;
  244. }
  245. #endif
  246. /* SPI chip select control */
  247. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  248. {
  249. return bus == 0 && cs < 2;
  250. }
  251. void spi_cs_activate(struct spi_slave *slave)
  252. {
  253. switch (slave->cs) {
  254. case 1:
  255. at91_set_gpio_output(AT91_PIN_PB18, 0);
  256. break;
  257. case 0:
  258. default:
  259. at91_set_gpio_output(AT91_PIN_PB3, 0);
  260. break;
  261. }
  262. }
  263. void spi_cs_deactivate(struct spi_slave *slave)
  264. {
  265. switch (slave->cs) {
  266. case 1:
  267. at91_set_gpio_output(AT91_PIN_PB18, 1);
  268. break;
  269. case 0:
  270. default:
  271. at91_set_gpio_output(AT91_PIN_PB3, 1);
  272. break;
  273. }
  274. }
  275. static struct atmel_serial_platdata at91sam9260_serial_plat = {
  276. .base_addr = ATMEL_BASE_DBGU,
  277. };
  278. U_BOOT_DEVICE(at91sam9260_serial) = {
  279. .name = "serial_atmel",
  280. .plat = &at91sam9260_serial_plat,
  281. };