eth.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <netdev.h>
  11. #include <fm_eth.h>
  12. #include <fsl_mdio.h>
  13. #include <malloc.h>
  14. #include <asm/types.h>
  15. #include <fsl_dtsec.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/arch-fsl-layerscape/config.h>
  18. #include <asm/arch-fsl-layerscape/immap_lsch2.h>
  19. #include <asm/arch/fsl_serdes.h>
  20. #include <linux/delay.h>
  21. #include <net/pfe_eth/pfe_eth.h>
  22. #include <dm/platform_data/pfe_dm_eth.h>
  23. #include <i2c.h>
  24. #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  25. static inline void ls1012ardb_reset_phy(void)
  26. {
  27. #ifdef CONFIG_TARGET_LS1012ARDB
  28. /* Through reset IO expander reset both RGMII and SGMII PHYs */
  29. #ifdef CONFIG_DM_I2C
  30. struct udevice *dev;
  31. int ret;
  32. /*
  33. * The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
  34. */
  35. ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
  36. 1, &dev);
  37. if (ret) {
  38. printf("%s: Cannot find udev for a bus %d\n", __func__,
  39. 0);
  40. return;
  41. }
  42. /* Config port 0
  43. * - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
  44. * are enabled as an output.
  45. */
  46. dm_i2c_reg_write(dev, 6, __PHY_MASK);
  47. /*
  48. * Set port 0 output a value to reset ETH2 interface
  49. * - pin IOXP_RST_ETH2_B output 0b0
  50. */
  51. dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
  52. mdelay(10);
  53. dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
  54. /*
  55. * Set port 0 output a value to reset ETH1 interface
  56. * - pin IOXP_RST_ETH1_B output 0b0
  57. */
  58. mdelay(10);
  59. dm_i2c_reg_write(dev, 2, 0xFF);
  60. #else
  61. i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
  62. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
  63. mdelay(10);
  64. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
  65. mdelay(10);
  66. i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
  67. #endif
  68. mdelay(50);
  69. #endif
  70. }
  71. int pfe_eth_board_init(struct udevice *dev)
  72. {
  73. static int init_done;
  74. struct mii_dev *bus;
  75. struct pfe_mdio_info mac_mdio_info;
  76. struct pfe_eth_dev *priv = dev_get_priv(dev);
  77. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  78. int srds_s1 = in_be32(&gur->rcwsr[4]) &
  79. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  80. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  81. if (!init_done) {
  82. ls1012ardb_reset_phy();
  83. mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
  84. mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  85. bus = pfe_mdio_init(&mac_mdio_info);
  86. if (!bus) {
  87. printf("Failed to register mdio\n");
  88. return -1;
  89. }
  90. init_done = 1;
  91. }
  92. pfe_set_mdio(priv->gemac_port,
  93. miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
  94. switch (srds_s1) {
  95. case 0x3508:
  96. if (!priv->gemac_port) {
  97. /* MAC1 */
  98. pfe_set_phy_address_mode(priv->gemac_port,
  99. CONFIG_PFE_EMAC1_PHY_ADDR,
  100. PHY_INTERFACE_MODE_SGMII);
  101. } else {
  102. /* MAC2 */
  103. pfe_set_phy_address_mode(priv->gemac_port,
  104. CONFIG_PFE_EMAC2_PHY_ADDR,
  105. PHY_INTERFACE_MODE_RGMII_ID);
  106. }
  107. break;
  108. case 0x2208:
  109. if (!priv->gemac_port) {
  110. /* MAC1 */
  111. pfe_set_phy_address_mode(priv->gemac_port,
  112. CONFIG_PFE_EMAC1_PHY_ADDR,
  113. PHY_INTERFACE_MODE_SGMII_2500);
  114. } else {
  115. /* MAC2 */
  116. pfe_set_phy_address_mode(priv->gemac_port,
  117. CONFIG_PFE_EMAC2_PHY_ADDR,
  118. PHY_INTERFACE_MODE_SGMII_2500);
  119. }
  120. break;
  121. default:
  122. printf("unsupported SerDes PRCTL= %d\n", srds_s1);
  123. break;
  124. }
  125. return 0;
  126. }
  127. static struct pfe_eth_pdata pfe_pdata0 = {
  128. .pfe_eth_pdata_mac = {
  129. .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
  130. .phy_interface = 0,
  131. },
  132. .pfe_ddr_addr = {
  133. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  134. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  135. },
  136. };
  137. static struct pfe_eth_pdata pfe_pdata1 = {
  138. .pfe_eth_pdata_mac = {
  139. .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
  140. .phy_interface = 1,
  141. },
  142. .pfe_ddr_addr = {
  143. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  144. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  145. },
  146. };
  147. U_BOOT_DEVICE(ls1012a_pfe0) = {
  148. .name = "pfe_eth",
  149. .plat = &pfe_pdata0,
  150. };
  151. U_BOOT_DEVICE(ls1012a_pfe1) = {
  152. .name = "pfe_eth",
  153. .plat = &pfe_pdata1,
  154. };