eth.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/io.h>
  9. #include <netdev.h>
  10. #include <fm_eth.h>
  11. #include <fsl_mdio.h>
  12. #include <malloc.h>
  13. #include <asm/types.h>
  14. #include <fsl_dtsec.h>
  15. #include <asm/arch/soc.h>
  16. #include <asm/arch-fsl-layerscape/config.h>
  17. #include <asm/arch-fsl-layerscape/immap_lsch2.h>
  18. #include <asm/arch/fsl_serdes.h>
  19. #include <linux/delay.h>
  20. #include "../common/qixis.h"
  21. #include <net/pfe_eth/pfe_eth.h>
  22. #include <dm/platform_data/pfe_dm_eth.h>
  23. #include "ls1012aqds_qixis.h"
  24. #define EMI_NONE 0xFF
  25. #define EMI1_RGMII 1
  26. #define EMI1_SLOT1 2
  27. #define EMI1_SLOT2 3
  28. #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  29. #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
  30. static const char * const mdio_names[] = {
  31. "NULL",
  32. "LS1012AQDS_MDIO_RGMII",
  33. "LS1012AQDS_MDIO_SLOT1",
  34. "LS1012AQDS_MDIO_SLOT2",
  35. "NULL",
  36. };
  37. static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
  38. {
  39. return mdio_names[muxval];
  40. }
  41. struct ls1012aqds_mdio {
  42. u8 muxval;
  43. struct mii_dev *realbus;
  44. };
  45. static void ls1012aqds_mux_mdio(u8 muxval)
  46. {
  47. u8 brdcfg4;
  48. if (muxval < 7) {
  49. brdcfg4 = QIXIS_READ(brdcfg[4]);
  50. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  51. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  52. QIXIS_WRITE(brdcfg[4], brdcfg4);
  53. }
  54. }
  55. static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  56. int regnum)
  57. {
  58. struct ls1012aqds_mdio *priv = bus->priv;
  59. ls1012aqds_mux_mdio(priv->muxval);
  60. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  61. }
  62. static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
  63. int regnum, u16 value)
  64. {
  65. struct ls1012aqds_mdio *priv = bus->priv;
  66. ls1012aqds_mux_mdio(priv->muxval);
  67. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  68. }
  69. static int ls1012aqds_mdio_reset(struct mii_dev *bus)
  70. {
  71. struct ls1012aqds_mdio *priv = bus->priv;
  72. if (priv->realbus->reset)
  73. return priv->realbus->reset(priv->realbus);
  74. else
  75. return -1;
  76. }
  77. static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
  78. {
  79. struct ls1012aqds_mdio *pmdio;
  80. struct mii_dev *bus = mdio_alloc();
  81. if (!bus) {
  82. printf("Failed to allocate ls1012aqds MDIO bus\n");
  83. return -1;
  84. }
  85. pmdio = malloc(sizeof(*pmdio));
  86. if (!pmdio) {
  87. printf("Failed to allocate ls1012aqds private data\n");
  88. free(bus);
  89. return -1;
  90. }
  91. bus->read = ls1012aqds_mdio_read;
  92. bus->write = ls1012aqds_mdio_write;
  93. bus->reset = ls1012aqds_mdio_reset;
  94. sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
  95. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  96. if (!pmdio->realbus) {
  97. printf("No bus with name %s\n", realbusname);
  98. free(bus);
  99. free(pmdio);
  100. return -1;
  101. }
  102. pmdio->muxval = muxval;
  103. bus->priv = pmdio;
  104. return mdio_register(bus);
  105. }
  106. int pfe_eth_board_init(struct udevice *dev)
  107. {
  108. static int init_done;
  109. struct mii_dev *bus;
  110. static const char *mdio_name;
  111. struct pfe_mdio_info mac_mdio_info;
  112. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  113. u8 data8;
  114. struct pfe_eth_dev *priv = dev_get_priv(dev);
  115. int srds_s1 = in_be32(&gur->rcwsr[4]) &
  116. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  117. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  118. ls1012aqds_mux_mdio(EMI1_SLOT1);
  119. if (!init_done) {
  120. mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
  121. mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  122. bus = pfe_mdio_init(&mac_mdio_info);
  123. if (!bus) {
  124. printf("Failed to register mdio\n");
  125. return -1;
  126. }
  127. init_done = 1;
  128. }
  129. if (priv->gemac_port) {
  130. mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
  131. mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
  132. bus = pfe_mdio_init(&mac_mdio_info);
  133. if (!bus) {
  134. printf("Failed to register mdio\n");
  135. return -1;
  136. }
  137. }
  138. switch (srds_s1) {
  139. case 0x3508:
  140. printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
  141. #ifdef CONFIG_PFE_RGMII_RESET_WA
  142. /*
  143. * Work around for FPGA registers initialization
  144. * This is needed for RGMII to work.
  145. */
  146. printf("Reset RGMII WA....\n");
  147. data8 = QIXIS_READ(rst_frc[0]);
  148. data8 |= 0x2;
  149. QIXIS_WRITE(rst_frc[0], data8);
  150. data8 = QIXIS_READ(rst_frc[0]);
  151. data8 = QIXIS_READ(res8[6]);
  152. data8 |= 0xff;
  153. QIXIS_WRITE(res8[6], data8);
  154. data8 = QIXIS_READ(res8[6]);
  155. #endif
  156. if (priv->gemac_port) {
  157. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
  158. if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
  159. < 0) {
  160. printf("Failed to register mdio for %s\n", mdio_name);
  161. }
  162. /* MAC2 */
  163. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
  164. bus = miiphy_get_dev_by_name(mdio_name);
  165. pfe_set_mdio(priv->gemac_port, bus);
  166. pfe_set_phy_address_mode(priv->gemac_port,
  167. CONFIG_PFE_EMAC2_PHY_ADDR,
  168. PHY_INTERFACE_MODE_RGMII);
  169. } else {
  170. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
  171. if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
  172. < 0) {
  173. printf("Failed to register mdio for %s\n", mdio_name);
  174. }
  175. /* MAC1 */
  176. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
  177. bus = miiphy_get_dev_by_name(mdio_name);
  178. pfe_set_mdio(priv->gemac_port, bus);
  179. pfe_set_phy_address_mode(priv->gemac_port,
  180. CONFIG_PFE_EMAC1_PHY_ADDR,
  181. PHY_INTERFACE_MODE_SGMII);
  182. }
  183. break;
  184. case 0x2205:
  185. printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
  186. /*
  187. * Work around for FPGA registers initialization
  188. * This is needed for RGMII to work.
  189. */
  190. printf("Reset SLOT1 SLOT2....\n");
  191. data8 = QIXIS_READ(rst_frc[2]);
  192. data8 |= 0xc0;
  193. QIXIS_WRITE(rst_frc[2], data8);
  194. mdelay(100);
  195. data8 = QIXIS_READ(rst_frc[2]);
  196. data8 &= 0x3f;
  197. QIXIS_WRITE(rst_frc[2], data8);
  198. if (priv->gemac_port) {
  199. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
  200. if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
  201. < 0) {
  202. printf("Failed to register mdio for %s\n", mdio_name);
  203. }
  204. /* MAC2 */
  205. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
  206. bus = miiphy_get_dev_by_name(mdio_name);
  207. pfe_set_mdio(1, bus);
  208. pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
  209. PHY_INTERFACE_MODE_SGMII_2500);
  210. data8 = QIXIS_READ(brdcfg[12]);
  211. data8 |= 0x20;
  212. QIXIS_WRITE(brdcfg[12], data8);
  213. } else {
  214. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
  215. if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
  216. < 0) {
  217. printf("Failed to register mdio for %s\n", mdio_name);
  218. }
  219. /* MAC1 */
  220. mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
  221. bus = miiphy_get_dev_by_name(mdio_name);
  222. pfe_set_mdio(0, bus);
  223. pfe_set_phy_address_mode(0,
  224. CONFIG_PFE_SGMII_2500_PHY1_ADDR,
  225. PHY_INTERFACE_MODE_SGMII_2500);
  226. }
  227. break;
  228. default:
  229. printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
  230. break;
  231. }
  232. return 0;
  233. }
  234. static struct pfe_eth_pdata pfe_pdata0 = {
  235. .pfe_eth_pdata_mac = {
  236. .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
  237. .phy_interface = 0,
  238. },
  239. .pfe_ddr_addr = {
  240. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  241. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  242. },
  243. };
  244. static struct pfe_eth_pdata pfe_pdata1 = {
  245. .pfe_eth_pdata_mac = {
  246. .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
  247. .phy_interface = 1,
  248. },
  249. .pfe_ddr_addr = {
  250. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  251. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  252. },
  253. };
  254. U_BOOT_DEVICE(ls1012a_pfe0) = {
  255. .name = "pfe_eth",
  256. .plat = &pfe_pdata0,
  257. };
  258. U_BOOT_DEVICE(ls1012a_pfe1) = {
  259. .name = "pfe_eth",
  260. .plat = &pfe_pdata1,
  261. };