eth.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <netdev.h>
  11. #include <fm_eth.h>
  12. #include <fsl_mdio.h>
  13. #include <malloc.h>
  14. #include <asm/types.h>
  15. #include <fsl_dtsec.h>
  16. #include <asm/arch/soc.h>
  17. #include <asm/arch-fsl-layerscape/config.h>
  18. #include <asm/arch-fsl-layerscape/immap_lsch2.h>
  19. #include <asm/arch/fsl_serdes.h>
  20. #include <linux/delay.h>
  21. #include <net/pfe_eth/pfe_eth.h>
  22. #include <dm/platform_data/pfe_dm_eth.h>
  23. #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
  24. #define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
  25. #define MASK_ETH_PHY_RST 0x00000100
  26. static inline void ls1012afrdm_reset_phy(void)
  27. {
  28. unsigned int val;
  29. struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
  30. setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
  31. val = in_be32(&pgpio->gpdat);
  32. setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
  33. mdelay(10);
  34. val = in_be32(&pgpio->gpdat);
  35. setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
  36. mdelay(50);
  37. }
  38. int pfe_eth_board_init(struct udevice *dev)
  39. {
  40. static int init_done;
  41. struct mii_dev *bus;
  42. struct pfe_mdio_info mac_mdio_info;
  43. struct pfe_eth_dev *priv = dev_get_priv(dev);
  44. if (!init_done) {
  45. ls1012afrdm_reset_phy();
  46. mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
  47. mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
  48. bus = pfe_mdio_init(&mac_mdio_info);
  49. if (!bus) {
  50. printf("Failed to register mdio\n");
  51. return -1;
  52. }
  53. init_done = 1;
  54. }
  55. if (priv->gemac_port) {
  56. mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
  57. mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
  58. bus = pfe_mdio_init(&mac_mdio_info);
  59. if (!bus) {
  60. printf("Failed to register mdio\n");
  61. return -1;
  62. }
  63. }
  64. pfe_set_mdio(priv->gemac_port,
  65. miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
  66. if (!priv->gemac_port)
  67. /* MAC1 */
  68. pfe_set_phy_address_mode(priv->gemac_port,
  69. CONFIG_PFE_EMAC1_PHY_ADDR,
  70. PHY_INTERFACE_MODE_SGMII);
  71. else
  72. /* MAC2 */
  73. pfe_set_phy_address_mode(priv->gemac_port,
  74. CONFIG_PFE_EMAC2_PHY_ADDR,
  75. PHY_INTERFACE_MODE_SGMII);
  76. return 0;
  77. }
  78. static struct pfe_eth_pdata pfe_pdata0 = {
  79. .pfe_eth_pdata_mac = {
  80. .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
  81. .phy_interface = 0,
  82. },
  83. .pfe_ddr_addr = {
  84. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  85. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  86. },
  87. };
  88. static struct pfe_eth_pdata pfe_pdata1 = {
  89. .pfe_eth_pdata_mac = {
  90. .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
  91. .phy_interface = 1,
  92. },
  93. .pfe_ddr_addr = {
  94. .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
  95. .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
  96. },
  97. };
  98. U_BOOT_DEVICE(ls1012a_pfe0) = {
  99. .name = "pfe_eth",
  100. .plat = &pfe_pdata0,
  101. };
  102. U_BOOT_DEVICE(ls1012a_pfe1) = {
  103. .name = "pfe_eth",
  104. .plat = &pfe_pdata1,
  105. };