thunderx.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * (C) Copyright 2014, Cavium Inc.
  4. **/
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <errno.h>
  11. #include <net.h>
  12. #include <linux/compiler.h>
  13. #include <cavium/atf.h>
  14. #include <asm/armv8/mmu.h>
  15. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  16. #include <dm/platform_data/serial_pl01x.h>
  17. static const struct pl01x_serial_platdata serial0 = {
  18. .base = CONFIG_SYS_SERIAL0,
  19. .type = TYPE_PL011,
  20. .clock = 0,
  21. .skip_init = true,
  22. };
  23. U_BOOT_DEVICE(thunderx_serial0) = {
  24. .name = "serial_pl01x",
  25. .plat = &serial0,
  26. };
  27. static const struct pl01x_serial_platdata serial1 = {
  28. .base = CONFIG_SYS_SERIAL1,
  29. .type = TYPE_PL011,
  30. .clock = 0,
  31. .skip_init = true,
  32. };
  33. U_BOOT_DEVICE(thunderx_serial1) = {
  34. .name = "serial_pl01x",
  35. .plat = &serial1,
  36. };
  37. #endif
  38. DECLARE_GLOBAL_DATA_PTR;
  39. static struct mm_region thunderx_mem_map[] = {
  40. {
  41. .virt = 0x000000000000UL,
  42. .phys = 0x000000000000UL,
  43. .size = 0x40000000000UL,
  44. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
  45. }, {
  46. .virt = 0x800000000000UL,
  47. .phys = 0x800000000000UL,
  48. .size = 0x40000000000UL,
  49. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  50. PTE_BLOCK_NON_SHARE,
  51. }, {
  52. .virt = 0x840000000000UL,
  53. .phys = 0x840000000000UL,
  54. .size = 0x40000000000UL,
  55. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56. PTE_BLOCK_NON_SHARE,
  57. }, {
  58. /* List terminator */
  59. 0,
  60. }
  61. };
  62. struct mm_region *mem_map = thunderx_mem_map;
  63. int board_init(void)
  64. {
  65. return 0;
  66. }
  67. int timer_init(void)
  68. {
  69. return 0;
  70. }
  71. int dram_init(void)
  72. {
  73. ssize_t node_count = atf_node_count();
  74. ssize_t dram_size;
  75. int node;
  76. printf("Initializing\nNodes in system: %zd\n", node_count);
  77. gd->ram_size = 0;
  78. for (node = 0; node < node_count; node++) {
  79. dram_size = atf_dram_size(node);
  80. printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
  81. gd->ram_size += dram_size;
  82. }
  83. gd->ram_size -= MEM_BASE;
  84. *(unsigned long *)CPU_RELEASE_ADDR = 0;
  85. puts("DRAM size:");
  86. return 0;
  87. }
  88. /*
  89. * Board specific reset that is system reset.
  90. */
  91. void reset_cpu(ulong addr)
  92. {
  93. }
  94. /*
  95. * Board specific ethernet initialization routine.
  96. */
  97. int board_eth_init(struct bd_info *bis)
  98. {
  99. int rc = 0;
  100. return rc;
  101. }
  102. #ifdef CONFIG_PCI
  103. void pci_init_board(void)
  104. {
  105. printf("DEBUG: PCI Init TODO *****\n");
  106. }
  107. #endif