intel_pinctrl.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017 Intel Corporation.
  4. * Copyright 2019 Google LLC
  5. *
  6. * Modified from coreboot gpio.h
  7. */
  8. #ifndef __ASM_INTEL_PINCTRL_H
  9. #define __ASM_INTEL_PINCTRL_H
  10. #include <dm/pinctrl.h>
  11. #include <linux/bitops.h>
  12. /**
  13. * struct pad_config - config for a pad
  14. * @pad: offset of pad within community
  15. * @pad_config: Pad config data corresponding to DW0, DW1, etc.
  16. */
  17. struct pad_config {
  18. int pad;
  19. u32 pad_config[4];
  20. };
  21. #include <asm/arch/gpio.h>
  22. /* GPIO community IOSF sideband clock gating */
  23. #define MISCCFG_GPSIDEDPCGEN BIT(5)
  24. /* GPIO community RCOMP clock gating */
  25. #define MISCCFG_GPRCOMPCDLCGEN BIT(4)
  26. /* GPIO community RTC clock gating */
  27. #define MISCCFG_GPRTCDLCGEN BIT(3)
  28. /* GFX controller clock gating */
  29. #define MISCCFG_GSXSLCGEN BIT(2)
  30. /* GPIO community partition clock gating */
  31. #define MISCCFG_GPDPCGEN BIT(1)
  32. /* GPIO community local clock gating */
  33. #define MISCCFG_GPDLCGEN BIT(0)
  34. /* Enable GPIO community power management configuration */
  35. #define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
  36. MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
  37. | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
  38. /*
  39. * GPIO numbers may not be contiguous and instead will have a different
  40. * starting pin number for each pad group.
  41. */
  42. #define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
  43. group_pad_base) \
  44. { \
  45. .first_pad = (start_of_group) - (first_of_community), \
  46. .size = (end_of_group) - (start_of_group) + 1, \
  47. .acpi_pad_base = (group_pad_base), \
  48. }
  49. /*
  50. * A pad base of -1 indicates that this group uses contiguous numbering
  51. * and a pad base should not be used for this group.
  52. */
  53. #define PAD_BASE_NONE -1
  54. /* The common/default group numbering is contiguous */
  55. #define INTEL_GPP(first_of_community, start_of_group, end_of_group) \
  56. INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
  57. PAD_BASE_NONE)
  58. /**
  59. * struct reset_mapping - logical to actual value for PADRSTCFG in DW0
  60. *
  61. * Note that the values are expected to be within the field placement of the
  62. * register itself. i.e. if the reset field is at 31:30 then the values within
  63. * logical and chipset should occupy 31:30.
  64. */
  65. struct reset_mapping {
  66. u32 logical;
  67. u32 chipset;
  68. };
  69. /**
  70. * struct pad_group - describes the groups within each community
  71. *
  72. * @first_pad: offset of first pad of the group relative to the community
  73. * @size: size of the group
  74. * @acpi_pad_base: starting pin number for the pads in this group when they are
  75. * used in ACPI. This is only needed if the pins are not contiguous across
  76. * groups. Most groups will have this set to PAD_BASE_NONE and use
  77. * contiguous numbering for ACPI.
  78. */
  79. struct pad_group {
  80. int first_pad;
  81. uint size;
  82. int acpi_pad_base;
  83. };
  84. /**
  85. * struct pad_community - community of pads
  86. *
  87. * This describes a community, or each group within a community when multiple
  88. * groups exist inside a community
  89. *
  90. * @name: Community name
  91. * @num_gpi_regs: number of gpi registers in community
  92. * @max_pads_per_group: number of pads in each group; number of pads bit-mapped
  93. * in each GPI status/en and Host Own Reg
  94. * @first_pad: first pad in community
  95. * @last_pad: last pad in community
  96. * @host_own_reg_0: offset to Host Ownership Reg 0
  97. * @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0
  98. * @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0
  99. * @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0
  100. * @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0
  101. * @pad_cfg_base: offset to first PAD_GFG_DW0 Reg
  102. * @gpi_status_offset: specifies offset in struct gpi_status
  103. * @port: PCR Port ID
  104. * @reset_map: PADRSTCFG logical to chipset mapping
  105. * @num_reset_vals: number of values in @reset_map
  106. * @groups; list of groups for this community
  107. * @num_groups: number of groups
  108. */
  109. struct pad_community {
  110. const char *name;
  111. size_t num_gpi_regs;
  112. size_t max_pads_per_group;
  113. uint first_pad;
  114. uint last_pad;
  115. u16 host_own_reg_0;
  116. u16 gpi_int_sts_reg_0;
  117. u16 gpi_int_en_reg_0;
  118. u16 gpi_smi_sts_reg_0;
  119. u16 gpi_smi_en_reg_0;
  120. u16 pad_cfg_base;
  121. u8 gpi_status_offset;
  122. u8 port;
  123. const struct reset_mapping *reset_map;
  124. size_t num_reset_vals;
  125. const struct pad_group *groups;
  126. size_t num_groups;
  127. };
  128. /**
  129. * struct intel_pinctrl_priv - private data for each pinctrl device
  130. *
  131. * @comm: Pad community for this device
  132. * @num_cfgs: Number of configuration words for each pad
  133. * @itss: ITSS device (for interrupt handling)
  134. * @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
  135. * Each bit represents IRQx Active High Polarity Disable configuration:
  136. * when set to 1, the interrupt polarity associated with IRQx is inverted
  137. * to appear as Active Low to IOAPIC and vice versa
  138. */
  139. struct intel_pinctrl_priv {
  140. const struct pad_community *comm;
  141. int num_cfgs;
  142. struct udevice *itss;
  143. bool itss_pol_cfg;
  144. };
  145. /* Exported common operations for the pinctrl driver */
  146. extern const struct pinctrl_ops intel_pinctrl_ops;
  147. /* Exported common probe function for the pinctrl driver */
  148. int intel_pinctrl_probe(struct udevice *dev);
  149. /**
  150. * intel_pinctrl_ofdata_to_platdata() - Handle common plat setup
  151. *
  152. * @dev: Pinctrl device
  153. * @comm: Pad community for this device
  154. * @num_cfgs: Number of configuration words for each pad
  155. * @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
  156. */
  157. int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
  158. const struct pad_community *comm,
  159. int num_cfgs);
  160. /**
  161. * pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
  162. *
  163. * The values from PMC register GPE_CFG are passed which is then mapped to
  164. * proper groups for MISCCFG. This basically sets the MISCCFG register bits:
  165. * dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
  166. * dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
  167. * dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
  168. *
  169. * @dev: ITSS device
  170. * @gpe0b: Value for GPE0B
  171. * @gpe0c: Value for GPE0C
  172. * @gpe0d: Value for GPE0D
  173. * @return 0 if OK, -ve on error
  174. */
  175. int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d);
  176. /**
  177. * pinctrl_config_pads() - Configure a list of pads
  178. *
  179. * Configures multiple pads using the provided data from the device tree.
  180. *
  181. * @dev: pinctrl device (any will do)
  182. * @pads: Pad data, consisting of a pad number followed by num_cfgs entries
  183. * containing the data for that pad (num_cfgs is set by the pinctrl device)
  184. * @pads_count: Number of pads to configure
  185. * @return 0 if OK, -ve on error
  186. */
  187. int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count);
  188. /**
  189. * pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use
  190. *
  191. * This enables the interrupt inputs and clears the status register bits
  192. *
  193. * @return 0 if OK, -ve on error
  194. */
  195. int pinctrl_gpi_clear_int_cfg(void);
  196. /**
  197. * pinctrl_config_pads_for_node() - Configure pads
  198. *
  199. * Set up the pads using the data in a given node
  200. *
  201. * @dev: pinctrl device (any will do)
  202. * @node: Node containing the 'pads' property with the data in it
  203. * @return 0 if OK, -ve on error
  204. */
  205. int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node);
  206. /**
  207. * pinctrl_read_pads() - Read pad data from a node
  208. *
  209. * @dev: pinctrl device (any will do, it is just used to get config)
  210. * @node: Node to read pad data from
  211. * @prop: Property name to use (e.g. "pads")
  212. * @padsp: Returns a pointer to an allocated array of pad data, in the format:
  213. * <pad>
  214. * <pad_config0>
  215. * <pad_config1>
  216. * ...
  217. *
  218. * The number of pad config values is set by the pinctrl controller.
  219. * The caller must free this array.
  220. * @pad_countp: Returns the number of pads read
  221. * @ereturn 0 if OK, -ve on error
  222. */
  223. int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
  224. u32 **padsp, int *pad_countp);
  225. /**
  226. * pinctrl_count_pads() - Count the number of pads in a pad array
  227. *
  228. * This used used with of-platdata where the array may be smaller than its
  229. * maximum size. This function searches for the last pad in the array by finding
  230. * the first 'zero' record
  231. *
  232. * This works out the number of records in the array. Each record has one word
  233. * for the pad and num_cfgs words for the config.
  234. *
  235. * @dev: pinctrl device (any will do)
  236. * @pads: Array of pad data
  237. * @size: Size of pad data in bytes
  238. * @return number of pads represented by the data
  239. */
  240. int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
  241. /**
  242. * intel_pinctrl_get_config_reg_offset() - Get offset of pin config registers
  243. *
  244. * This works out the register offset of a pin within the p2sb region.
  245. *
  246. * @dev: Pinctrl device
  247. * @offset: GPIO offset within this device
  248. * @return register offset of first register within the GPIO p2sb region
  249. */
  250. u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset);
  251. /**
  252. * intel_pinctrl_get_config_reg_addr() - Get address of pin config registers
  253. *
  254. * This works out the absolute address of the registers for a pin
  255. * @dev: Pinctrl device
  256. * @offset: GPIO offset within this device
  257. * @return register address of first register within the GPIO p2sb region
  258. */
  259. u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
  260. /**
  261. * intel_pinctrl_get_config_reg() - Get the value of a GPIO register
  262. *
  263. * @dev: Pinctrl device
  264. * @offset: GPIO offset within this device
  265. * @return register value within the GPIO p2sb region
  266. */
  267. u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
  268. /**
  269. * intel_pinctrl_get_pad() - Get pad information for a pad
  270. *
  271. * This is used by the GPIO controller to find the pinctrl used by a pad.
  272. *
  273. * @pad: Pad to check
  274. * @devp: Returns pinctrl device containing that pad
  275. * @offsetp: Returns offset of pad within that pinctrl device
  276. * @return 0 if OK, -ENOTBLK if pad number is invalid
  277. */
  278. int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
  279. /**
  280. * intel_pinctrl_get_acpi_pin() - Get the ACPI pin for a pinctrl pin
  281. *
  282. * Maps a pinctrl pin (in terms of its offset within the pins controlled by that
  283. * pinctrl) to an ACPI GPIO pin-table entry.
  284. *
  285. * @dev: Pinctrl device to check
  286. * @offset: Offset of pin within that device (0 = first)
  287. * @return associated ACPI GPIO pin-table entry, or standard pin number if the
  288. * ACPI pad base is not set
  289. */
  290. int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset);
  291. #endif