mp_init.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. *
  5. * Based on code from the coreboot file of the same name
  6. */
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <qfw.h>
  14. #include <asm/atomic.h>
  15. #include <asm/cpu.h>
  16. #include <asm/interrupt.h>
  17. #include <asm/io.h>
  18. #include <asm/lapic.h>
  19. #include <asm/microcode.h>
  20. #include <asm/mp.h>
  21. #include <asm/msr.h>
  22. #include <asm/mtrr.h>
  23. #include <asm/processor.h>
  24. #include <asm/sipi.h>
  25. #include <dm/device-internal.h>
  26. #include <dm/uclass-internal.h>
  27. #include <dm/lists.h>
  28. #include <dm/root.h>
  29. #include <linux/delay.h>
  30. #include <linux/linkage.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. /*
  33. * Setting up multiprocessing
  34. *
  35. * See https://www.intel.com/content/www/us/en/intelligent-systems/intel-boot-loader-development-kit/minimal-intel-architecture-boot-loader-paper.html
  36. *
  37. * Note that this file refers to the boot CPU (the one U-Boot is running on) as
  38. * the BSP (BootStrap Processor) and the others as APs (Application Processors).
  39. *
  40. * This module works by loading some setup code into RAM at AP_DEFAULT_BASE and
  41. * telling each AP to execute it. The code that each AP runs is in
  42. * sipi_vector.S (see ap_start16) which includes a struct sipi_params at the
  43. * end of it. Those parameters are set up by the C code.
  44. * Setting up is handled by load_sipi_vector(). It inits the common block of
  45. * parameters (sipi_params) which tell the APs what to do. This block includes
  46. * microcode and the MTTRs (Memory-Type-Range Registers) from the main CPU.
  47. * There is also an ap_count which each AP increments as it starts up, so the
  48. * BSP can tell how many checked in.
  49. *
  50. * The APs are started with a SIPI (Startup Inter-Processor Interrupt) which
  51. * tells an AP to start executing at a particular address, in this case
  52. * AP_DEFAULT_BASE which contains the code copied from ap_start16. This protocol
  53. * is handled by start_aps().
  54. *
  55. * After being started, each AP runs the code in ap_start16, switches to 32-bit
  56. * mode, runs the code at ap_start, then jumps to c_handler which is ap_init().
  57. * This runs a very simple 'flight plan' described in mp_steps(). This sets up
  58. * the CPU and waits for further instructions by looking at its entry in
  59. * ap_callbacks[]. Note that the flight plan is only actually run for each CPU
  60. * in bsp_do_flight_plan(): once the BSP completes each flight record, it sets
  61. * mp_flight_record->barrier to 1 to allow the APs to executed the record one
  62. * by one.
  63. *
  64. * CPUS are numbered sequentially from 0 using the device tree:
  65. *
  66. * cpus {
  67. * u-boot,dm-pre-reloc;
  68. * #address-cells = <1>;
  69. * #size-cells = <0>;
  70. *
  71. * cpu@0 {
  72. * u-boot,dm-pre-reloc;
  73. * device_type = "cpu";
  74. * compatible = "intel,apl-cpu";
  75. * reg = <0>;
  76. * intel,apic-id = <0>;
  77. * };
  78. *
  79. * cpu@1 {
  80. * device_type = "cpu";
  81. * compatible = "intel,apl-cpu";
  82. * reg = <1>;
  83. * intel,apic-id = <2>;
  84. * };
  85. *
  86. * Here the 'reg' property is the CPU number and then is placed in dev->req_seq
  87. * so that we can index into ap_callbacks[] using that. The APIC ID is different
  88. * and may not be sequential (it typically is if hyperthreading is supported).
  89. *
  90. * Once APs are inited they wait in ap_wait_for_instruction() for instructions.
  91. * Instructions come in the form of a function to run. This logic is in
  92. * mp_run_on_cpus() which supports running on any one AP, all APs, just the BSP
  93. * or all CPUs. The BSP logic is handled directly in mp_run_on_cpus(), by
  94. * calling the function. For the APs, callback information is stored in a
  95. * single, common struct mp_callback and a pointer to this is written to each
  96. * AP's slot in ap_callbacks[] by run_ap_work(). All APs get the message even
  97. * if it is only for one of them. When an AP notices a message it checks whether
  98. * it should call the function (see check in ap_wait_for_instruction()) and then
  99. * does so if needed. After that it sets its slot to NULL to indicate it is
  100. * done.
  101. *
  102. * While U-Boot is running it can use mp_run_on_cpus() to run code on the APs.
  103. * An example of this is the 'mtrr' command which allows reading and changing
  104. * the MTRRs on all CPUs.
  105. *
  106. * Before U-Boot exits it calls mp_park_aps() which tells all CPUs to halt by
  107. * executing a 'hlt' instruction. That allows them to be used by Linux when it
  108. * starts up.
  109. */
  110. /* This also needs to match the sipi.S assembly code for saved MSR encoding */
  111. struct __packed saved_msr {
  112. uint32_t index;
  113. uint32_t lo;
  114. uint32_t hi;
  115. };
  116. /**
  117. * struct mp_flight_plan - Holds the flight plan
  118. *
  119. * @num_records: Number of flight records
  120. * @records: Pointer to each record
  121. */
  122. struct mp_flight_plan {
  123. int num_records;
  124. struct mp_flight_record *records;
  125. };
  126. /**
  127. * struct mp_callback - Callback information for APs
  128. *
  129. * @func: Function to run
  130. * @arg: Argument to pass to the function
  131. * @logical_cpu_number: Either a CPU number (i.e. dev->req_seq) or a special
  132. * value like MP_SELECT_BSP. It tells the AP whether it should process this
  133. * callback
  134. */
  135. struct mp_callback {
  136. mp_run_func func;
  137. void *arg;
  138. int logical_cpu_number;
  139. };
  140. /* Stores the flight plan so that APs can find it */
  141. static struct mp_flight_plan mp_info;
  142. /*
  143. * ap_callbacks - Callback mailbox array
  144. *
  145. * Array of callback, one entry for each available CPU, indexed by the CPU
  146. * number, which is dev->req_seq. The entry for the main CPU is never used.
  147. * When this is NULL, there is no pending work for the CPU to run. When
  148. * non-NULL it points to the mp_callback structure. This is shared between all
  149. * CPUs, so should only be written by the main CPU.
  150. */
  151. static struct mp_callback **ap_callbacks;
  152. static inline void barrier_wait(atomic_t *b)
  153. {
  154. while (atomic_read(b) == 0)
  155. asm("pause");
  156. mfence();
  157. }
  158. static inline void release_barrier(atomic_t *b)
  159. {
  160. mfence();
  161. atomic_set(b, 1);
  162. }
  163. static inline void stop_this_cpu(void)
  164. {
  165. /* Called by an AP when it is ready to halt and wait for a new task */
  166. for (;;)
  167. cpu_hlt();
  168. }
  169. /* Returns 1 if timeout waiting for APs. 0 if target APs found */
  170. static int wait_for_aps(atomic_t *val, int target, int total_delay,
  171. int delay_step)
  172. {
  173. int timeout = 0;
  174. int delayed = 0;
  175. while (atomic_read(val) != target) {
  176. udelay(delay_step);
  177. delayed += delay_step;
  178. if (delayed >= total_delay) {
  179. timeout = 1;
  180. break;
  181. }
  182. }
  183. return timeout;
  184. }
  185. static void ap_do_flight_plan(struct udevice *cpu)
  186. {
  187. int i;
  188. for (i = 0; i < mp_info.num_records; i++) {
  189. struct mp_flight_record *rec = &mp_info.records[i];
  190. atomic_inc(&rec->cpus_entered);
  191. barrier_wait(&rec->barrier);
  192. if (rec->ap_call != NULL)
  193. rec->ap_call(cpu, rec->ap_arg);
  194. }
  195. }
  196. static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
  197. {
  198. struct udevice *dev;
  199. *devp = NULL;
  200. for (uclass_find_first_device(UCLASS_CPU, &dev);
  201. dev;
  202. uclass_find_next_device(&dev)) {
  203. struct cpu_platdata *plat = dev_get_parent_plat(dev);
  204. if (plat->cpu_id == apic_id) {
  205. *devp = dev;
  206. return 0;
  207. }
  208. }
  209. return -ENOENT;
  210. }
  211. /*
  212. * By the time APs call ap_init() caching has been setup, and microcode has
  213. * been loaded
  214. */
  215. static void ap_init(unsigned int cpu_index)
  216. {
  217. struct udevice *dev;
  218. int apic_id;
  219. int ret;
  220. /* Ensure the local apic is enabled */
  221. enable_lapic();
  222. apic_id = lapicid();
  223. ret = find_cpu_by_apic_id(apic_id, &dev);
  224. if (ret) {
  225. debug("Unknown CPU apic_id %x\n", apic_id);
  226. goto done;
  227. }
  228. debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
  229. dev ? dev->name : "(apic_id not found)");
  230. /*
  231. * Walk the flight plan, which only returns if CONFIG_SMP_AP_WORK is not
  232. * enabled
  233. */
  234. ap_do_flight_plan(dev);
  235. done:
  236. stop_this_cpu();
  237. }
  238. static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
  239. MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
  240. MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
  241. MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
  242. MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
  243. };
  244. static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
  245. {
  246. msr_t msr;
  247. msr = msr_read(index);
  248. entry->index = index;
  249. entry->lo = msr.lo;
  250. entry->hi = msr.hi;
  251. /* Return the next entry */
  252. entry++;
  253. return entry;
  254. }
  255. static int save_bsp_msrs(char *start, int size)
  256. {
  257. int msr_count;
  258. int num_var_mtrrs;
  259. struct saved_msr *msr_entry;
  260. int i;
  261. msr_t msr;
  262. /* Determine number of MTRRs need to be saved */
  263. msr = msr_read(MTRR_CAP_MSR);
  264. num_var_mtrrs = msr.lo & 0xff;
  265. /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
  266. msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
  267. if ((msr_count * sizeof(struct saved_msr)) > size) {
  268. printf("Cannot mirror all %d msrs\n", msr_count);
  269. return -ENOSPC;
  270. }
  271. msr_entry = (void *)start;
  272. for (i = 0; i < NUM_FIXED_MTRRS; i++)
  273. msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
  274. for (i = 0; i < num_var_mtrrs; i++) {
  275. msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
  276. msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
  277. }
  278. msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
  279. return msr_count;
  280. }
  281. static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
  282. {
  283. struct sipi_params_16bit *params16;
  284. struct sipi_params *params;
  285. static char msr_save[512];
  286. char *stack;
  287. ulong addr;
  288. int code_len;
  289. int size;
  290. int ret;
  291. /* Copy in the code */
  292. code_len = ap_start16_code_end - ap_start16;
  293. debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
  294. code_len);
  295. memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
  296. addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
  297. params16 = (struct sipi_params_16bit *)addr;
  298. params16->ap_start = (uint32_t)ap_start;
  299. params16->gdt = (uint32_t)gd->arch.gdt;
  300. params16->gdt_limit = X86_GDT_SIZE - 1;
  301. debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
  302. params = (struct sipi_params *)sipi_params;
  303. debug("SIPI 32-bit params at %p\n", params);
  304. params->idt_ptr = (uint32_t)x86_get_idt();
  305. params->stack_size = CONFIG_AP_STACK_SIZE;
  306. size = params->stack_size * num_cpus;
  307. stack = memalign(4096, size);
  308. if (!stack)
  309. return -ENOMEM;
  310. params->stack_top = (u32)(stack + size);
  311. #if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
  312. !defined(CONFIG_INTEL_MID)
  313. params->microcode_ptr = ucode_base;
  314. debug("Microcode at %x\n", params->microcode_ptr);
  315. #endif
  316. params->msr_table_ptr = (u32)msr_save;
  317. ret = save_bsp_msrs(msr_save, sizeof(msr_save));
  318. if (ret < 0)
  319. return ret;
  320. params->msr_count = ret;
  321. params->c_handler = (uint32_t)&ap_init;
  322. *ap_countp = &params->ap_count;
  323. atomic_set(*ap_countp, 0);
  324. debug("SIPI vector is ready\n");
  325. return 0;
  326. }
  327. static int check_cpu_devices(int expected_cpus)
  328. {
  329. int i;
  330. for (i = 0; i < expected_cpus; i++) {
  331. struct udevice *dev;
  332. int ret;
  333. ret = uclass_find_device(UCLASS_CPU, i, &dev);
  334. if (ret) {
  335. debug("Cannot find CPU %d in device tree\n", i);
  336. return ret;
  337. }
  338. }
  339. return 0;
  340. }
  341. /* Returns 1 for timeout. 0 on success */
  342. static int apic_wait_timeout(int total_delay, const char *msg)
  343. {
  344. int total = 0;
  345. if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
  346. return 0;
  347. debug("Waiting for %s...", msg);
  348. while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
  349. udelay(50);
  350. total += 50;
  351. if (total >= total_delay) {
  352. debug("timed out: aborting\n");
  353. return -ETIMEDOUT;
  354. }
  355. }
  356. debug("done\n");
  357. return 0;
  358. }
  359. /**
  360. * start_aps() - Start up the APs and count how many we find
  361. *
  362. * This is called on the boot processor to start up all the other processors
  363. * (here called APs).
  364. *
  365. * @num_aps: Number of APs we expect to find
  366. * @ap_count: Initially zero. Incremented by this function for each AP found
  367. * @return 0 if all APs were set up correctly or there are none to set up,
  368. * -ENOSPC if the SIPI vector is too high in memory,
  369. * -ETIMEDOUT if the ICR is busy or the second SIPI fails to complete
  370. * -EIO if not all APs check in correctly
  371. */
  372. static int start_aps(int num_aps, atomic_t *ap_count)
  373. {
  374. int sipi_vector;
  375. /* Max location is 4KiB below 1MiB */
  376. const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
  377. if (num_aps == 0)
  378. return 0;
  379. /* The vector is sent as a 4k aligned address in one byte */
  380. sipi_vector = AP_DEFAULT_BASE >> 12;
  381. if (sipi_vector > max_vector_loc) {
  382. printf("SIPI vector too large! 0x%08x\n",
  383. sipi_vector);
  384. return -ENOSPC;
  385. }
  386. debug("Attempting to start %d APs\n", num_aps);
  387. if (apic_wait_timeout(1000, "ICR not to be busy"))
  388. return -ETIMEDOUT;
  389. /* Send INIT IPI to all but self */
  390. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  391. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  392. LAPIC_DM_INIT);
  393. debug("Waiting for 10ms after sending INIT\n");
  394. mdelay(10);
  395. /* Send 1st SIPI */
  396. if (apic_wait_timeout(1000, "ICR not to be busy"))
  397. return -ETIMEDOUT;
  398. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  399. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  400. LAPIC_DM_STARTUP | sipi_vector);
  401. if (apic_wait_timeout(10000, "first SIPI to complete"))
  402. return -ETIMEDOUT;
  403. /* Wait for CPUs to check in up to 200 us */
  404. wait_for_aps(ap_count, num_aps, 200, 15);
  405. /* Send 2nd SIPI */
  406. if (apic_wait_timeout(1000, "ICR not to be busy"))
  407. return -ETIMEDOUT;
  408. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  409. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  410. LAPIC_DM_STARTUP | sipi_vector);
  411. if (apic_wait_timeout(10000, "second SIPI to complete"))
  412. return -ETIMEDOUT;
  413. /* Wait for CPUs to check in */
  414. if (wait_for_aps(ap_count, num_aps, 10000, 50)) {
  415. debug("Not all APs checked in: %d/%d\n",
  416. atomic_read(ap_count), num_aps);
  417. return -EIO;
  418. }
  419. return 0;
  420. }
  421. /**
  422. * bsp_do_flight_plan() - Do the flight plan on the BSP
  423. *
  424. * This runs the flight plan on the main CPU used to boot U-Boot
  425. *
  426. * @cpu: Device for the main CPU
  427. * @plan: Flight plan to run
  428. * @num_aps: Number of APs (CPUs other than the BSP)
  429. * @returns 0 on success, -ETIMEDOUT if an AP failed to come up
  430. */
  431. static int bsp_do_flight_plan(struct udevice *cpu, struct mp_flight_plan *plan,
  432. int num_aps)
  433. {
  434. int i;
  435. int ret = 0;
  436. const int timeout_us = 100000;
  437. const int step_us = 100;
  438. for (i = 0; i < plan->num_records; i++) {
  439. struct mp_flight_record *rec = &plan->records[i];
  440. /* Wait for APs if the record is not released */
  441. if (atomic_read(&rec->barrier) == 0) {
  442. /* Wait for the APs to check in */
  443. if (wait_for_aps(&rec->cpus_entered, num_aps,
  444. timeout_us, step_us)) {
  445. debug("MP record %d timeout\n", i);
  446. ret = -ETIMEDOUT;
  447. }
  448. }
  449. if (rec->bsp_call != NULL)
  450. rec->bsp_call(cpu, rec->bsp_arg);
  451. release_barrier(&rec->barrier);
  452. }
  453. return ret;
  454. }
  455. /**
  456. * get_bsp() - Get information about the bootstrap processor
  457. *
  458. * @devp: If non-NULL, returns CPU device corresponding to the BSP
  459. * @cpu_countp: If non-NULL, returns the total number of CPUs
  460. * @return CPU number of the BSP, or -ve on error. If multiprocessing is not
  461. * enabled, returns 0
  462. */
  463. static int get_bsp(struct udevice **devp, int *cpu_countp)
  464. {
  465. char processor_name[CPU_MAX_NAME_LEN];
  466. struct udevice *dev;
  467. int apic_id;
  468. int ret;
  469. cpu_get_name(processor_name);
  470. debug("CPU: %s\n", processor_name);
  471. apic_id = lapicid();
  472. ret = find_cpu_by_apic_id(apic_id, &dev);
  473. if (ret < 0) {
  474. printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
  475. return ret;
  476. }
  477. ret = cpu_get_count(dev);
  478. if (ret < 0)
  479. return log_msg_ret("count", ret);
  480. if (devp)
  481. *devp = dev;
  482. if (cpu_countp)
  483. *cpu_countp = ret;
  484. return dev->req_seq >= 0 ? dev->req_seq : 0;
  485. }
  486. /**
  487. * read_callback() - Read the pointer in a callback slot
  488. *
  489. * This is called by APs to read their callback slot to see if there is a
  490. * pointer to new instructions
  491. *
  492. * @slot: Pointer to the AP's callback slot
  493. * @return value of that pointer
  494. */
  495. static struct mp_callback *read_callback(struct mp_callback **slot)
  496. {
  497. dmb();
  498. return *slot;
  499. }
  500. /**
  501. * store_callback() - Store a pointer to the callback slot
  502. *
  503. * This is called by APs to write NULL into the callback slot when they have
  504. * finished the work requested by the BSP.
  505. *
  506. * @slot: Pointer to the AP's callback slot
  507. * @val: Value to write (e.g. NULL)
  508. */
  509. static void store_callback(struct mp_callback **slot, struct mp_callback *val)
  510. {
  511. *slot = val;
  512. dmb();
  513. }
  514. /**
  515. * run_ap_work() - Run a callback on selected APs
  516. *
  517. * This writes @callback to all APs and waits for them all to acknowledge it,
  518. * Note that whether each AP actually calls the callback depends on the value
  519. * of logical_cpu_number (see struct mp_callback). The logical CPU number is
  520. * the CPU device's req->seq value.
  521. *
  522. * @callback: Callback information to pass to all APs
  523. * @bsp: CPU device for the BSP
  524. * @num_cpus: The number of CPUs in the system (= number of APs + 1)
  525. * @expire_ms: Timeout to wait for all APs to finish, in milliseconds, or 0 for
  526. * no timeout
  527. * @return 0 if OK, -ETIMEDOUT if one or more APs failed to respond in time
  528. */
  529. static int run_ap_work(struct mp_callback *callback, struct udevice *bsp,
  530. int num_cpus, uint expire_ms)
  531. {
  532. int cur_cpu = bsp->req_seq;
  533. int num_aps = num_cpus - 1; /* number of non-BSPs to get this message */
  534. int cpus_accepted;
  535. ulong start;
  536. int i;
  537. if (!IS_ENABLED(CONFIG_SMP_AP_WORK)) {
  538. printf("APs already parked. CONFIG_SMP_AP_WORK not enabled\n");
  539. return -ENOTSUPP;
  540. }
  541. /* Signal to all the APs to run the func. */
  542. for (i = 0; i < num_cpus; i++) {
  543. if (cur_cpu != i)
  544. store_callback(&ap_callbacks[i], callback);
  545. }
  546. mfence();
  547. /* Wait for all the APs to signal back that call has been accepted. */
  548. start = get_timer(0);
  549. do {
  550. mdelay(1);
  551. cpus_accepted = 0;
  552. for (i = 0; i < num_cpus; i++) {
  553. if (cur_cpu == i)
  554. continue;
  555. if (!read_callback(&ap_callbacks[i]))
  556. cpus_accepted++;
  557. }
  558. if (expire_ms && get_timer(start) >= expire_ms) {
  559. log(UCLASS_CPU, LOGL_CRIT,
  560. "AP call expired; %d/%d CPUs accepted\n",
  561. cpus_accepted, num_aps);
  562. return -ETIMEDOUT;
  563. }
  564. } while (cpus_accepted != num_aps);
  565. /* Make sure we can see any data written by the APs */
  566. mfence();
  567. return 0;
  568. }
  569. /**
  570. * ap_wait_for_instruction() - Wait for and process requests from the main CPU
  571. *
  572. * This is called by APs (here, everything other than the main boot CPU) to
  573. * await instructions. They arrive in the form of a function call and argument,
  574. * which is then called. This uses a simple mailbox with atomic read/set
  575. *
  576. * @cpu: CPU that is waiting
  577. * @unused: Optional argument provided by struct mp_flight_record, not used here
  578. * @return Does not return
  579. */
  580. static int ap_wait_for_instruction(struct udevice *cpu, void *unused)
  581. {
  582. struct mp_callback lcb;
  583. struct mp_callback **per_cpu_slot;
  584. if (!IS_ENABLED(CONFIG_SMP_AP_WORK))
  585. return 0;
  586. per_cpu_slot = &ap_callbacks[cpu->req_seq];
  587. while (1) {
  588. struct mp_callback *cb = read_callback(per_cpu_slot);
  589. if (!cb) {
  590. asm ("pause");
  591. continue;
  592. }
  593. /* Copy to local variable before using the value */
  594. memcpy(&lcb, cb, sizeof(lcb));
  595. mfence();
  596. if (lcb.logical_cpu_number == MP_SELECT_ALL ||
  597. lcb.logical_cpu_number == MP_SELECT_APS ||
  598. cpu->req_seq == lcb.logical_cpu_number)
  599. lcb.func(lcb.arg);
  600. /* Indicate we are finished */
  601. store_callback(per_cpu_slot, NULL);
  602. }
  603. return 0;
  604. }
  605. static int mp_init_cpu(struct udevice *cpu, void *unused)
  606. {
  607. struct cpu_platdata *plat = dev_get_parent_plat(cpu);
  608. plat->ucode_version = microcode_read_rev();
  609. plat->device_id = gd->arch.x86_device;
  610. return device_probe(cpu);
  611. }
  612. static struct mp_flight_record mp_steps[] = {
  613. MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
  614. MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL, NULL, NULL),
  615. };
  616. int mp_run_on_cpus(int cpu_select, mp_run_func func, void *arg)
  617. {
  618. struct mp_callback lcb = {
  619. .func = func,
  620. .arg = arg,
  621. .logical_cpu_number = cpu_select,
  622. };
  623. struct udevice *dev;
  624. int num_cpus;
  625. int ret;
  626. ret = get_bsp(&dev, &num_cpus);
  627. if (ret < 0)
  628. return log_msg_ret("bsp", ret);
  629. if (cpu_select == MP_SELECT_ALL || cpu_select == MP_SELECT_BSP ||
  630. cpu_select == ret) {
  631. /* Run on BSP first */
  632. func(arg);
  633. }
  634. if (!IS_ENABLED(CONFIG_SMP_AP_WORK) ||
  635. !(gd->flags & GD_FLG_SMP_READY)) {
  636. /* Allow use of this function on the BSP only */
  637. if (cpu_select == MP_SELECT_BSP || !cpu_select)
  638. return 0;
  639. return -ENOTSUPP;
  640. }
  641. /* Allow up to 1 second for all APs to finish */
  642. ret = run_ap_work(&lcb, dev, num_cpus, 1000 /* ms */);
  643. if (ret)
  644. return log_msg_ret("aps", ret);
  645. return 0;
  646. }
  647. static void park_this_cpu(void *unused)
  648. {
  649. stop_this_cpu();
  650. }
  651. int mp_park_aps(void)
  652. {
  653. int ret;
  654. ret = mp_run_on_cpus(MP_SELECT_APS, park_this_cpu, NULL);
  655. if (ret)
  656. return log_ret(ret);
  657. return 0;
  658. }
  659. int mp_first_cpu(int cpu_select)
  660. {
  661. struct udevice *dev;
  662. int num_cpus;
  663. int ret;
  664. /*
  665. * This assumes that CPUs are numbered from 0. This function tries to
  666. * avoid assuming the CPU 0 is the boot CPU
  667. */
  668. if (cpu_select == MP_SELECT_ALL)
  669. return 0; /* start with the first one */
  670. ret = get_bsp(&dev, &num_cpus);
  671. if (ret < 0)
  672. return log_msg_ret("bsp", ret);
  673. /* Return boot CPU if requested */
  674. if (cpu_select == MP_SELECT_BSP)
  675. return ret;
  676. /* Return something other than the boot CPU, if APs requested */
  677. if (cpu_select == MP_SELECT_APS && num_cpus > 1)
  678. return ret == 0 ? 1 : 0;
  679. /* Try to check for an invalid value */
  680. if (cpu_select < 0 || cpu_select >= num_cpus)
  681. return -EINVAL;
  682. return cpu_select; /* return the only selected one */
  683. }
  684. int mp_next_cpu(int cpu_select, int prev_cpu)
  685. {
  686. struct udevice *dev;
  687. int num_cpus;
  688. int ret;
  689. int bsp;
  690. /* If we selected the BSP or a particular single CPU, we are done */
  691. if (!IS_ENABLED(CONFIG_SMP_AP_WORK) || cpu_select == MP_SELECT_BSP ||
  692. cpu_select >= 0)
  693. return -EFBIG;
  694. /* Must be doing MP_SELECT_ALL or MP_SELECT_APS; return the next CPU */
  695. ret = get_bsp(&dev, &num_cpus);
  696. if (ret < 0)
  697. return log_msg_ret("bsp", ret);
  698. bsp = ret;
  699. /* Move to the next CPU */
  700. assert(prev_cpu >= 0);
  701. ret = prev_cpu + 1;
  702. /* Skip the BSP if needed */
  703. if (cpu_select == MP_SELECT_APS && ret == bsp)
  704. ret++;
  705. if (ret >= num_cpus)
  706. return -EFBIG;
  707. return ret;
  708. }
  709. int mp_init(void)
  710. {
  711. int num_aps, num_cpus;
  712. atomic_t *ap_count;
  713. struct udevice *cpu;
  714. struct uclass *uc;
  715. int ret;
  716. if (IS_ENABLED(CONFIG_QFW)) {
  717. ret = qemu_cpu_fixup();
  718. if (ret)
  719. return ret;
  720. }
  721. /*
  722. * Multiple APs are brought up simultaneously and they may get the same
  723. * seq num in the uclass_resolve_seq() during device_probe(). To avoid
  724. * this, set req_seq to the reg number in the device tree in advance.
  725. */
  726. uclass_id_foreach_dev(UCLASS_CPU, cpu, uc)
  727. cpu->req_seq = dev_read_u32_default(cpu, "reg", -1);
  728. ret = get_bsp(&cpu, &num_cpus);
  729. if (ret < 0) {
  730. debug("Cannot init boot CPU: err=%d\n", ret);
  731. return ret;
  732. }
  733. if (num_cpus < 2)
  734. debug("Warning: Only 1 CPU is detected\n");
  735. ret = check_cpu_devices(num_cpus);
  736. if (ret)
  737. log_warning("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
  738. ap_callbacks = calloc(num_cpus, sizeof(struct mp_callback *));
  739. if (!ap_callbacks)
  740. return -ENOMEM;
  741. /* Copy needed parameters so that APs have a reference to the plan */
  742. mp_info.num_records = ARRAY_SIZE(mp_steps);
  743. mp_info.records = mp_steps;
  744. /* Load the SIPI vector */
  745. ret = load_sipi_vector(&ap_count, num_cpus);
  746. if (ap_count == NULL)
  747. return -ENOENT;
  748. /*
  749. * Make sure SIPI data hits RAM so the APs that come up will see
  750. * the startup code even if the caches are disabled
  751. */
  752. wbinvd();
  753. /* Start the APs providing number of APs and the cpus_entered field */
  754. num_aps = num_cpus - 1;
  755. ret = start_aps(num_aps, ap_count);
  756. if (ret) {
  757. mdelay(1000);
  758. debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
  759. num_aps);
  760. return ret;
  761. }
  762. /* Walk the flight plan for the BSP */
  763. ret = bsp_do_flight_plan(cpu, &mp_info, num_aps);
  764. if (ret) {
  765. debug("CPU init failed: err=%d\n", ret);
  766. return ret;
  767. }
  768. gd->flags |= GD_FLG_SMP_READY;
  769. return 0;
  770. }