p2sb.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Primary-to-Sideband Bridge
  4. *
  5. * Copyright 2019 Google LLC
  6. */
  7. #define LOG_CATEGORY UCLASS_P2SB
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <log.h>
  12. #include <p2sb.h>
  13. #include <spl.h>
  14. #include <asm/pci.h>
  15. #include <linux/bitops.h>
  16. #define PCH_P2SB_E0 0xe0
  17. #define HIDE_BIT BIT(0)
  18. struct p2sb_platdata {
  19. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  20. struct dtd_intel_p2sb dtplat;
  21. #endif
  22. ulong mmio_base;
  23. pci_dev_t bdf;
  24. };
  25. /* PCI config space registers */
  26. #define HPTC_OFFSET 0x60
  27. #define HPTC_ADDR_ENABLE_BIT BIT(7)
  28. /* High Performance Event Timer Configuration */
  29. #define P2SB_HPTC 0x60
  30. #define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
  31. /*
  32. * ADDRESS_SELECT ENCODING_RANGE
  33. * 0 0xfed0 0000 - 0xfed0 03ff
  34. * 1 0xfed0 1000 - 0xfed0 13ff
  35. * 2 0xfed0 2000 - 0xfed0 23ff
  36. * 3 0xfed0 3000 - 0xfed0 33ff
  37. */
  38. #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
  39. #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
  40. #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
  41. #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
  42. /*
  43. * p2sb_early_init() - Enable decoding for HPET range
  44. *
  45. * This is needed by FSP-M which uses the High Precision Event Timer.
  46. *
  47. * @dev: P2SB device
  48. * @return 0 if OK, -ve on error
  49. */
  50. static int p2sb_early_init(struct udevice *dev)
  51. {
  52. struct p2sb_platdata *plat = dev_get_platdata(dev);
  53. pci_dev_t pdev = plat->bdf;
  54. /*
  55. * Enable decoding for HPET memory address range.
  56. * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
  57. * the High Performance Timer memory address range
  58. * selected by bits 1:0
  59. */
  60. pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
  61. PCI_SIZE_8);
  62. /* Enable PCR Base address in PCH */
  63. pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
  64. PCI_SIZE_32);
  65. pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  66. /* Enable P2SB MSE */
  67. pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
  68. PCI_COMMAND_MEMORY, PCI_SIZE_8);
  69. return 0;
  70. }
  71. static int p2sb_spl_init(struct udevice *dev)
  72. {
  73. /* Enable decoding for HPET. Needed for FSP global pointer storage */
  74. dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
  75. P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
  76. return 0;
  77. }
  78. int p2sb_ofdata_to_platdata(struct udevice *dev)
  79. {
  80. struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
  81. struct p2sb_platdata *plat = dev_get_platdata(dev);
  82. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  83. int ret;
  84. u32 base[2];
  85. ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
  86. if (ret)
  87. return log_msg_ret("Missing/short early-regs", ret);
  88. plat->mmio_base = base[0];
  89. /* TPL sets up the initial BAR */
  90. if (spl_phase() == PHASE_TPL) {
  91. plat->bdf = pci_get_devfn(dev);
  92. if (plat->bdf < 0)
  93. return log_msg_ret("Cannot get p2sb PCI address",
  94. plat->bdf);
  95. }
  96. upriv->mmio_base = plat->mmio_base;
  97. #else
  98. plat->mmio_base = plat->dtplat.early_regs[0];
  99. plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
  100. upriv->mmio_base = plat->mmio_base;
  101. #endif
  102. return 0;
  103. }
  104. static int p2sb_probe(struct udevice *dev)
  105. {
  106. if (spl_phase() == PHASE_TPL)
  107. return p2sb_early_init(dev);
  108. else if (spl_phase() == PHASE_SPL)
  109. return p2sb_spl_init(dev);
  110. return 0;
  111. }
  112. static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
  113. {
  114. dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
  115. hide ? HIDE_BIT : 0);
  116. }
  117. static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
  118. {
  119. u16 vendor;
  120. if (!CONFIG_IS_ENABLED(PCI))
  121. return -EPERM;
  122. p2sb_set_hide_bit(dev, hide);
  123. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  124. if (hide && vendor != 0xffff)
  125. return log_msg_ret("hide", -EEXIST);
  126. else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
  127. return log_msg_ret("unhide", -ENOMEDIUM);
  128. return 0;
  129. }
  130. static int p2sb_remove(struct udevice *dev)
  131. {
  132. int ret;
  133. ret = intel_p2sb_set_hide(dev, true);
  134. if (ret)
  135. return log_msg_ret("hide", ret);
  136. return 0;
  137. }
  138. static int p2sb_child_post_bind(struct udevice *dev)
  139. {
  140. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  141. struct p2sb_child_platdata *pplat = dev_get_parent_plat(dev);
  142. int ret;
  143. u32 pid;
  144. ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
  145. if (ret)
  146. return ret;
  147. pplat->pid = pid;
  148. #endif
  149. return 0;
  150. }
  151. struct p2sb_ops p2sb_ops = {
  152. .set_hide = intel_p2sb_set_hide,
  153. };
  154. static const struct udevice_id p2sb_ids[] = {
  155. { .compatible = "intel,p2sb" },
  156. { }
  157. };
  158. U_BOOT_DRIVER(intel_p2sb) = {
  159. .name = "intel_p2sb",
  160. .id = UCLASS_P2SB,
  161. .of_match = p2sb_ids,
  162. .probe = p2sb_probe,
  163. .remove = p2sb_remove,
  164. .ops = &p2sb_ops,
  165. .ofdata_to_platdata = p2sb_ofdata_to_platdata,
  166. .plat_auto = sizeof(struct p2sb_platdata),
  167. .per_child_plat_auto =
  168. sizeof(struct p2sb_child_platdata),
  169. .child_post_bind = p2sb_child_post_bind,
  170. .flags = DM_FLAG_OS_PREPARE,
  171. };