sata.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. *
  5. * From coreboot src/soc/intel/broadwell/sata.c
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <asm/gpio.h>
  11. #include <asm/io.h>
  12. #include <asm/intel_regs.h>
  13. #include <asm/lpc_common.h>
  14. #include <asm/pch_common.h>
  15. #include <asm/pch_common.h>
  16. #include <asm/arch/pch.h>
  17. #include <linux/delay.h>
  18. struct sata_platdata {
  19. int port_map;
  20. uint port0_gen3_tx;
  21. uint port1_gen3_tx;
  22. uint port0_gen3_dtle;
  23. uint port1_gen3_dtle;
  24. /*
  25. * SATA DEVSLP Mux
  26. * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
  27. * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
  28. */
  29. int devslp_mux;
  30. /*
  31. * DEVSLP Disable
  32. * 0: DEVSLP is enabled
  33. * 1: DEVSLP is disabled
  34. */
  35. int devslp_disable;
  36. };
  37. static void broadwell_sata_init(struct udevice *dev)
  38. {
  39. struct sata_platdata *plat = dev_get_platdata(dev);
  40. u32 reg32;
  41. u8 *abar;
  42. u16 reg16;
  43. int port;
  44. debug("SATA: Initializing controller in AHCI mode.\n");
  45. /* Set timings */
  46. dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
  47. dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
  48. /* for AHCI, Port Enable is managed in memory mapped space */
  49. dm_pci_read_config16(dev, 0x92, &reg16);
  50. reg16 &= ~0xf;
  51. reg16 |= 0x8000 | plat->port_map;
  52. dm_pci_write_config16(dev, 0x92, reg16);
  53. udelay(2);
  54. /* Setup register 98h */
  55. dm_pci_read_config32(dev, 0x98, &reg32);
  56. reg32 &= ~((1 << 31) | (1 << 30));
  57. reg32 |= 1 << 23;
  58. reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
  59. dm_pci_write_config32(dev, 0x98, reg32);
  60. /* Setup register 9Ch */
  61. reg16 = 0; /* Disable alternate ID */
  62. reg16 = 1 << 5; /* BWG step 12 */
  63. dm_pci_write_config16(dev, 0x9c, reg16);
  64. /* SATA Initialization register */
  65. reg32 = 0x183;
  66. reg32 |= (plat->port_map ^ 0xf) << 24;
  67. reg32 |= (plat->devslp_mux & 1) << 15;
  68. dm_pci_write_config32(dev, 0x94, reg32);
  69. /* Initialize AHCI memory-mapped space */
  70. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, &reg32);
  71. abar = (u8 *)reg32;
  72. debug("ABAR: %p\n", abar);
  73. /* CAP (HBA Capabilities) : enable power management */
  74. clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
  75. 0x0c006000 /* PSC+SSC+SALP+SSS */ |
  76. 1 << 18); /* SAM: SATA AHCI MODE ONLY */
  77. /* PI (Ports implemented) */
  78. writel(plat->port_map, abar + 0x0c);
  79. (void) readl(abar + 0x0c); /* Read back 1 */
  80. (void) readl(abar + 0x0c); /* Read back 2 */
  81. /* CAP2 (HBA Capabilities Extended)*/
  82. if (plat->devslp_disable) {
  83. clrbits_le32(abar + 0x24, 1 << 3);
  84. } else {
  85. /* Enable DEVSLP */
  86. setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
  87. for (port = 0; port < 4; port++) {
  88. if (!(plat->port_map & (1 << port)))
  89. continue;
  90. /* DEVSLP DSP */
  91. setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
  92. }
  93. }
  94. /* Static Power Gating for unused ports */
  95. reg32 = readl(RCB_REG(0x3a84));
  96. /* Port 3 and 2 disabled */
  97. if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
  98. reg32 |= (1 << 24) | (1 << 26);
  99. /* Port 1 and 0 disabled */
  100. if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
  101. reg32 |= (1 << 20) | (1 << 18);
  102. writel(reg32, RCB_REG(0x3a84));
  103. /* Set Gen3 Transmitter settings if needed */
  104. if (plat->port0_gen3_tx)
  105. pch_iobp_update(SATA_IOBP_SP0_SECRT88,
  106. ~(SATA_SECRT88_VADJ_MASK <<
  107. SATA_SECRT88_VADJ_SHIFT),
  108. (plat->port0_gen3_tx &
  109. SATA_SECRT88_VADJ_MASK)
  110. << SATA_SECRT88_VADJ_SHIFT);
  111. if (plat->port1_gen3_tx)
  112. pch_iobp_update(SATA_IOBP_SP1_SECRT88,
  113. ~(SATA_SECRT88_VADJ_MASK <<
  114. SATA_SECRT88_VADJ_SHIFT),
  115. (plat->port1_gen3_tx &
  116. SATA_SECRT88_VADJ_MASK)
  117. << SATA_SECRT88_VADJ_SHIFT);
  118. /* Set Gen3 DTLE DATA / EDGE registers if needed */
  119. if (plat->port0_gen3_dtle) {
  120. pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
  121. ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
  122. (plat->port0_gen3_dtle & SATA_DTLE_MASK)
  123. << SATA_DTLE_DATA_SHIFT);
  124. pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
  125. ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
  126. (plat->port0_gen3_dtle & SATA_DTLE_MASK)
  127. << SATA_DTLE_EDGE_SHIFT);
  128. }
  129. if (plat->port1_gen3_dtle) {
  130. pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
  131. ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
  132. (plat->port1_gen3_dtle & SATA_DTLE_MASK)
  133. << SATA_DTLE_DATA_SHIFT);
  134. pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
  135. ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
  136. (plat->port1_gen3_dtle & SATA_DTLE_MASK)
  137. << SATA_DTLE_EDGE_SHIFT);
  138. }
  139. /*
  140. * Additional Programming Requirements for Power Optimizer
  141. */
  142. /* Step 1 */
  143. pch_common_sir_write(dev, 0x64, 0x883c9003);
  144. /* Step 2: SIR 68h[15:0] = 880Ah */
  145. reg32 = pch_common_sir_read(dev, 0x68);
  146. reg32 &= 0xffff0000;
  147. reg32 |= 0x880a;
  148. pch_common_sir_write(dev, 0x68, reg32);
  149. /* Step 3: SIR 60h[3] = 1 */
  150. reg32 = pch_common_sir_read(dev, 0x60);
  151. reg32 |= (1 << 3);
  152. pch_common_sir_write(dev, 0x60, reg32);
  153. /* Step 4: SIR 60h[0] = 1 */
  154. reg32 = pch_common_sir_read(dev, 0x60);
  155. reg32 |= (1 << 0);
  156. pch_common_sir_write(dev, 0x60, reg32);
  157. /* Step 5: SIR 60h[1] = 1 */
  158. reg32 = pch_common_sir_read(dev, 0x60);
  159. reg32 |= (1 << 1);
  160. pch_common_sir_write(dev, 0x60, reg32);
  161. /* Clock Gating */
  162. pch_common_sir_write(dev, 0x70, 0x3f00bf1f);
  163. pch_common_sir_write(dev, 0x54, 0xcf000f0f);
  164. pch_common_sir_write(dev, 0x58, 0x00190000);
  165. clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
  166. dm_pci_read_config32(dev, 0x300, &reg32);
  167. reg32 |= 1 << 17 | 1 << 16 | 1 << 19;
  168. reg32 |= 1 << 31 | 1 << 30 | 1 << 29;
  169. dm_pci_write_config32(dev, 0x300, reg32);
  170. dm_pci_read_config32(dev, 0x98, &reg32);
  171. reg32 |= 1 << 29;
  172. dm_pci_write_config32(dev, 0x98, reg32);
  173. /* Register Lock */
  174. dm_pci_read_config32(dev, 0x9c, &reg32);
  175. reg32 |= 1 << 31;
  176. dm_pci_write_config32(dev, 0x9c, reg32);
  177. }
  178. static int broadwell_sata_enable(struct udevice *dev)
  179. {
  180. struct sata_platdata *plat = dev_get_platdata(dev);
  181. struct gpio_desc desc;
  182. u16 map;
  183. int ret;
  184. /*
  185. * Set SATA controller mode early so the resource allocator can
  186. * properly assign IO/Memory resources for the controller.
  187. */
  188. map = 0x0060;
  189. map |= (plat->port_map ^ 0x3f) << 8;
  190. dm_pci_write_config16(dev, 0x90, map);
  191. ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT);
  192. if (ret)
  193. return ret;
  194. return 0;
  195. }
  196. static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
  197. {
  198. struct sata_platdata *plat = dev_get_platdata(dev);
  199. const void *blob = gd->fdt_blob;
  200. int node = dev_of_offset(dev);
  201. plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
  202. plat->port0_gen3_tx = fdtdec_get_int(blob, node,
  203. "intel,sata-port0-gen3-tx", 0);
  204. return 0;
  205. }
  206. static int broadwell_sata_probe(struct udevice *dev)
  207. {
  208. if (!(gd->flags & GD_FLG_RELOC))
  209. return broadwell_sata_enable(dev);
  210. else
  211. broadwell_sata_init(dev);
  212. return 0;
  213. }
  214. static const struct udevice_id broadwell_ahci_ids[] = {
  215. { .compatible = "intel,wildcatpoint-ahci" },
  216. { }
  217. };
  218. U_BOOT_DRIVER(ahci_broadwell_drv) = {
  219. .name = "ahci_broadwell",
  220. .id = UCLASS_AHCI,
  221. .of_match = broadwell_ahci_ids,
  222. .ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
  223. .probe = broadwell_sata_probe,
  224. .plat_auto = sizeof(struct sata_platdata),
  225. };