pwr_regulator.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <syscon.h>
  9. #include <asm/io.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/bitops.h>
  12. #include <linux/err.h>
  13. #include <power/pmic.h>
  14. #include <power/regulator.h>
  15. #define STM32MP_PWR_CR3 0xc
  16. #define STM32MP_PWR_CR3_USB33DEN BIT(24)
  17. #define STM32MP_PWR_CR3_USB33RDY BIT(26)
  18. #define STM32MP_PWR_CR3_REG18DEN BIT(28)
  19. #define STM32MP_PWR_CR3_REG18RDY BIT(29)
  20. #define STM32MP_PWR_CR3_REG11DEN BIT(30)
  21. #define STM32MP_PWR_CR3_REG11RDY BIT(31)
  22. struct stm32mp_pwr_reg_info {
  23. u32 enable;
  24. u32 ready;
  25. char *name;
  26. };
  27. struct stm32mp_pwr_priv {
  28. fdt_addr_t base;
  29. };
  30. static int stm32mp_pwr_write(struct udevice *dev, uint reg,
  31. const uint8_t *buff, int len)
  32. {
  33. struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
  34. u32 val = *(u32 *)buff;
  35. if (len != 4)
  36. return -EINVAL;
  37. writel(val, priv->base + STM32MP_PWR_CR3);
  38. return 0;
  39. }
  40. static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
  41. int len)
  42. {
  43. struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
  44. if (len != 4)
  45. return -EINVAL;
  46. *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3);
  47. return 0;
  48. }
  49. static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
  50. {
  51. struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
  52. priv->base = dev_read_addr(dev);
  53. if (priv->base == FDT_ADDR_T_NONE)
  54. return -EINVAL;
  55. return 0;
  56. }
  57. static const struct pmic_child_info pwr_children_info[] = {
  58. { .prefix = "reg", .driver = "stm32mp_pwr_regulator"},
  59. { .prefix = "usb", .driver = "stm32mp_pwr_regulator"},
  60. { },
  61. };
  62. static int stm32mp_pwr_bind(struct udevice *dev)
  63. {
  64. int children;
  65. children = pmic_bind_children(dev, dev->node, pwr_children_info);
  66. if (!children)
  67. dev_dbg(dev, "no child found\n");
  68. return 0;
  69. }
  70. static struct dm_pmic_ops stm32mp_pwr_ops = {
  71. .read = stm32mp_pwr_read,
  72. .write = stm32mp_pwr_write,
  73. };
  74. static const struct udevice_id stm32mp_pwr_ids[] = {
  75. { .compatible = "st,stm32mp1,pwr-reg" },
  76. { }
  77. };
  78. U_BOOT_DRIVER(stm32mp_pwr_pmic) = {
  79. .name = "stm32mp_pwr_pmic",
  80. .id = UCLASS_PMIC,
  81. .of_match = stm32mp_pwr_ids,
  82. .bind = stm32mp_pwr_bind,
  83. .ops = &stm32mp_pwr_ops,
  84. .ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
  85. .priv_auto = sizeof(struct stm32mp_pwr_priv),
  86. };
  87. static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
  88. .enable = STM32MP_PWR_CR3_REG11DEN,
  89. .ready = STM32MP_PWR_CR3_REG11RDY,
  90. .name = "reg11"
  91. };
  92. static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = {
  93. .enable = STM32MP_PWR_CR3_REG18DEN,
  94. .ready = STM32MP_PWR_CR3_REG18RDY,
  95. .name = "reg18"
  96. };
  97. static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = {
  98. .enable = STM32MP_PWR_CR3_USB33DEN,
  99. .ready = STM32MP_PWR_CR3_USB33RDY,
  100. .name = "usb33"
  101. };
  102. static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = {
  103. &stm32mp_pwr_reg11,
  104. &stm32mp_pwr_reg18,
  105. &stm32mp_pwr_usb33,
  106. NULL
  107. };
  108. static int stm32mp_pwr_regulator_probe(struct udevice *dev)
  109. {
  110. const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos;
  111. struct dm_regulator_uclass_plat *uc_pdata;
  112. uc_pdata = dev_get_uclass_plat(dev);
  113. while (*p) {
  114. int rc;
  115. rc = dev_read_stringlist_search(dev, "regulator-name",
  116. (*p)->name);
  117. if (rc >= 0) {
  118. dev_dbg(dev, "found regulator %s\n", (*p)->name);
  119. break;
  120. } else if (rc != -ENODATA) {
  121. return rc;
  122. }
  123. p++;
  124. }
  125. if (!*p) {
  126. int i = 0;
  127. const char *s;
  128. dev_dbg(dev, "regulator ");
  129. while (dev_read_string_index(dev, "regulator-name",
  130. i++, &s) >= 0)
  131. dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s);
  132. dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is");
  133. return -EINVAL;
  134. }
  135. uc_pdata->type = REGULATOR_TYPE_FIXED;
  136. dev->priv = (void *)*p;
  137. return 0;
  138. }
  139. static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
  140. {
  141. struct dm_regulator_uclass_plat *uc_pdata;
  142. uc_pdata = dev_get_uclass_plat(dev);
  143. if (!uc_pdata)
  144. return -ENXIO;
  145. if (uc_pdata->min_uV != uV) {
  146. dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name);
  147. return -EINVAL;
  148. }
  149. return 0;
  150. }
  151. static int stm32mp_pwr_regulator_get_value(struct udevice *dev)
  152. {
  153. struct dm_regulator_uclass_plat *uc_pdata;
  154. uc_pdata = dev_get_uclass_plat(dev);
  155. if (!uc_pdata)
  156. return -ENXIO;
  157. if (uc_pdata->min_uV != uc_pdata->max_uV) {
  158. dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name);
  159. return -EINVAL;
  160. }
  161. return uc_pdata->min_uV;
  162. }
  163. static int stm32mp_pwr_regulator_get_enable(struct udevice *dev)
  164. {
  165. const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev);
  166. int rc;
  167. u32 reg;
  168. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  169. if (rc)
  170. return rc;
  171. dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off");
  172. return (reg & p->enable) != 0;
  173. }
  174. static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable)
  175. {
  176. const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev);
  177. int rc;
  178. u32 reg;
  179. u32 time_start;
  180. dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name);
  181. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  182. if (rc)
  183. return rc;
  184. /* if regulator is already in the wanted state, nothing to do */
  185. if (!!(reg & p->enable) == enable)
  186. return 0;
  187. reg &= ~p->enable;
  188. if (enable)
  189. reg |= p->enable;
  190. rc = pmic_write(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  191. if (rc)
  192. return rc;
  193. if (!enable)
  194. return 0;
  195. /* waiting ready for enable */
  196. time_start = get_timer(0);
  197. while (1) {
  198. rc = pmic_read(dev->parent, 0, (uint8_t *)&reg, sizeof(reg));
  199. if (rc)
  200. return rc;
  201. if (reg & p->ready)
  202. break;
  203. if (get_timer(time_start) > CONFIG_SYS_HZ) {
  204. dev_dbg(dev, "%s: timeout\n", p->name);
  205. return -ETIMEDOUT;
  206. }
  207. }
  208. return 0;
  209. }
  210. static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = {
  211. .set_value = stm32mp_pwr_regulator_set_value,
  212. .get_value = stm32mp_pwr_regulator_get_value,
  213. .get_enable = stm32mp_pwr_regulator_get_enable,
  214. .set_enable = stm32mp_pwr_regulator_set_enable,
  215. };
  216. U_BOOT_DRIVER(stm32mp_pwr_regulator) = {
  217. .name = "stm32mp_pwr_regulator",
  218. .id = UCLASS_REGULATOR,
  219. .ops = &stm32mp_pwr_regulator_ops,
  220. .probe = stm32mp_pwr_regulator_probe,
  221. };