soc.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/mach-imx/dma.h>
  12. #include <asm/mach-imx/hab.h>
  13. #include <asm/mach-imx/rdc-sema.h>
  14. #include <asm/arch/imx-rdc.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <dm.h>
  18. #include <env.h>
  19. #include <imx_thermal.h>
  20. #include <fsl_sec.h>
  21. #include <asm/setup.h>
  22. #include <linux/delay.h>
  23. #define IOMUXC_GPR1 0x4
  24. #define BM_IOMUXC_GPR1_IRQ 0x1000
  25. #define GPC_LPCR_A7_BSC 0x0
  26. #define GPC_LPCR_M4 0x8
  27. #define GPC_SLPCR 0x14
  28. #define GPC_PGC_ACK_SEL_A7 0x24
  29. #define GPC_IMR1_CORE0 0x30
  30. #define GPC_IMR1_CORE1 0x40
  31. #define GPC_IMR1_M4 0x50
  32. #define GPC_PGC_CPU_MAPPING 0xec
  33. #define GPC_PGC_C0_PUPSCR 0x804
  34. #define GPC_PGC_SCU_TIMING 0x890
  35. #define GPC_PGC_C1_PUPSCR 0x844
  36. #define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
  37. #define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
  38. #define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
  39. #define BM_SLPCR_EN_DSM 0x80000000
  40. #define BM_SLPCR_RBC_EN 0x40000000
  41. #define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
  42. #define BM_SLPCR_VSTBY 0x4
  43. #define BM_SLPCR_SBYOS 0x2
  44. #define BM_SLPCR_BYPASS_PMIC_READY 0x1
  45. #define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
  46. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
  47. #define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
  48. #define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
  49. #if defined(CONFIG_IMX_THERMAL)
  50. static const struct imx_thermal_plat imx7_thermal_plat = {
  51. .regs = (void *)ANATOP_BASE_ADDR,
  52. .fuse_bank = 3,
  53. .fuse_word = 3,
  54. };
  55. U_BOOT_DEVICE(imx7_thermal) = {
  56. .name = "imx_thermal",
  57. .plat = &imx7_thermal_plat,
  58. };
  59. #endif
  60. #if CONFIG_IS_ENABLED(IMX_RDC)
  61. /*
  62. * In current design, if any peripheral was assigned to both A7 and M4,
  63. * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
  64. * low power mode. So M4 sleep will cause some peripherals fail to work
  65. * at A7 core side. At default, all resources are in domain 0 - 3.
  66. *
  67. * There are 26 peripherals impacted by this IC issue:
  68. * SIM2(sim2/emvsim2)
  69. * SIM1(sim1/emvsim1)
  70. * UART1/UART2/UART3/UART4/UART5/UART6/UART7
  71. * SAI1/SAI2/SAI3
  72. * WDOG1/WDOG2/WDOG3/WDOG4
  73. * GPT1/GPT2/GPT3/GPT4
  74. * PWM1/PWM2/PWM3/PWM4
  75. * ENET1/ENET2
  76. * Software Workaround:
  77. * Here we setup some resources to domain 0 where M4 codes will move
  78. * the M4 out of this domain. Then M4 is not able to access them any longer.
  79. * This is a workaround for ic issue. So the peripherals are not shared
  80. * by them. This way requires the uboot implemented the RDC driver and
  81. * set the 26 IPs above to domain 0 only. M4 code will assign resource
  82. * to its own domain, if it want to use the resource.
  83. */
  84. static rdc_peri_cfg_t const resources[] = {
  85. (RDC_PER_SIM1 | RDC_DOMAIN(0)),
  86. (RDC_PER_SIM2 | RDC_DOMAIN(0)),
  87. (RDC_PER_UART1 | RDC_DOMAIN(0)),
  88. (RDC_PER_UART2 | RDC_DOMAIN(0)),
  89. (RDC_PER_UART3 | RDC_DOMAIN(0)),
  90. (RDC_PER_UART4 | RDC_DOMAIN(0)),
  91. (RDC_PER_UART5 | RDC_DOMAIN(0)),
  92. (RDC_PER_UART6 | RDC_DOMAIN(0)),
  93. (RDC_PER_UART7 | RDC_DOMAIN(0)),
  94. (RDC_PER_SAI1 | RDC_DOMAIN(0)),
  95. (RDC_PER_SAI2 | RDC_DOMAIN(0)),
  96. (RDC_PER_SAI3 | RDC_DOMAIN(0)),
  97. (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
  98. (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
  99. (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
  100. (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
  101. (RDC_PER_GPT1 | RDC_DOMAIN(0)),
  102. (RDC_PER_GPT2 | RDC_DOMAIN(0)),
  103. (RDC_PER_GPT3 | RDC_DOMAIN(0)),
  104. (RDC_PER_GPT4 | RDC_DOMAIN(0)),
  105. (RDC_PER_PWM1 | RDC_DOMAIN(0)),
  106. (RDC_PER_PWM2 | RDC_DOMAIN(0)),
  107. (RDC_PER_PWM3 | RDC_DOMAIN(0)),
  108. (RDC_PER_PWM4 | RDC_DOMAIN(0)),
  109. (RDC_PER_ENET1 | RDC_DOMAIN(0)),
  110. (RDC_PER_ENET2 | RDC_DOMAIN(0)),
  111. };
  112. static void isolate_resource(void)
  113. {
  114. imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
  115. }
  116. #endif
  117. #if defined(CONFIG_IMX_HAB)
  118. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  119. .bank = 1,
  120. .word = 3,
  121. };
  122. #endif
  123. static bool is_mx7d(void)
  124. {
  125. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  126. struct fuse_bank *bank = &ocotp->bank[1];
  127. struct fuse_bank1_regs *fuse =
  128. (struct fuse_bank1_regs *)bank->fuse_regs;
  129. int val;
  130. val = readl(&fuse->tester4);
  131. if (val & 1)
  132. return false;
  133. else
  134. return true;
  135. }
  136. u32 get_cpu_rev(void)
  137. {
  138. struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
  139. ANATOP_BASE_ADDR;
  140. u32 reg = readl(&ccm_anatop->digprog);
  141. u32 type = (reg >> 16) & 0xff;
  142. if (!is_mx7d())
  143. type = MXC_CPU_MX7S;
  144. reg &= 0xff;
  145. return (type << 12) | reg;
  146. }
  147. #ifdef CONFIG_REVISION_TAG
  148. u32 __weak get_board_rev(void)
  149. {
  150. return get_cpu_rev();
  151. }
  152. #endif
  153. static void imx_enet_mdio_fixup(void)
  154. {
  155. struct iomuxc_gpr_base_regs *gpr_regs =
  156. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  157. /*
  158. * The management data input/output (MDIO) requires open-drain,
  159. * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
  160. * this feature. So to TO1.1, need to enable open drain by setting
  161. * bits GPR0[8:7].
  162. */
  163. if (soc_rev() >= CHIP_REV_1_1) {
  164. setbits_le32(&gpr_regs->gpr[0],
  165. IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
  166. }
  167. }
  168. static void init_cpu_basic(void)
  169. {
  170. imx_enet_mdio_fixup();
  171. #ifdef CONFIG_APBH_DMA
  172. /* Start APBH DMA */
  173. mxs_dma_init();
  174. #endif
  175. }
  176. #ifdef CONFIG_IMX_BOOTAUX
  177. /*
  178. * Table of mappings of physical mem regions in both
  179. * Cortex-A7 and Cortex-M4 address spaces.
  180. *
  181. * For additional details check sections 2.1.2 and 2.1.3 in
  182. * i.MX7Dual Applications Processor Reference Manual
  183. *
  184. */
  185. const struct rproc_att hostmap[] = {
  186. /* aux core , host core, size */
  187. { 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
  188. { 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
  189. { 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
  190. { 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
  191. { 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
  192. { 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
  193. { 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
  194. { 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
  195. { 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
  196. { 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
  197. { 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
  198. { 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
  199. { 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
  200. { /* sentinel */ }
  201. };
  202. #endif
  203. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  204. /* enable all periherial can be accessed in nosec mode */
  205. static void init_csu(void)
  206. {
  207. int i = 0;
  208. for (i = 0; i < CSU_NUM_REGS; i++)
  209. writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
  210. }
  211. static void imx_gpcv2_init(void)
  212. {
  213. u32 val, i;
  214. /*
  215. * Force IOMUXC irq pending, so that the interrupt to GPC can be
  216. * used to deassert dsm_request signal when the signal gets
  217. * asserted unexpectedly.
  218. */
  219. val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  220. val |= BM_IOMUXC_GPR1_IRQ;
  221. writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
  222. /* Initially mask all interrupts */
  223. for (i = 0; i < 4; i++) {
  224. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
  225. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
  226. writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
  227. }
  228. /* set SCU timing */
  229. writel((0x59 << 10) | 0x5B | (0x2 << 20),
  230. GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
  231. /* only external IRQs to wake up LPM and core 0/1 */
  232. val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  233. val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
  234. writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
  235. /* set C0 power up timming per design requirement */
  236. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  237. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  238. val |= (0x1A << 7);
  239. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
  240. /* set C1 power up timming per design requirement */
  241. val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  242. val &= ~BM_GPC_PGC_CORE_PUPSCR;
  243. val |= (0x1A << 7);
  244. writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
  245. /* dummy ack for time slot by default */
  246. writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
  247. BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
  248. GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
  249. /* mask M4 DSM trigger */
  250. writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
  251. BM_LPCR_M4_MASK_DSM_TRIGGER,
  252. GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
  253. /* set mega/fast mix in A7 domain */
  254. writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
  255. /* DSM related settings */
  256. val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
  257. val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
  258. BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
  259. BM_SLPCR_REG_BYPASS_COUNT);
  260. val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
  261. writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
  262. /*
  263. * disabling RBC need to delay at least 2 cycles of CKIL(32K)
  264. * due to hardware design requirement, which is
  265. * ~61us, here we use 65us for safe
  266. */
  267. udelay(65);
  268. }
  269. int arch_cpu_init(void)
  270. {
  271. init_aips();
  272. init_csu();
  273. /* Disable PDE bit of WMCR register */
  274. imx_wdog_disable_powerdown();
  275. init_cpu_basic();
  276. #if CONFIG_IS_ENABLED(IMX_RDC)
  277. isolate_resource();
  278. #endif
  279. init_snvs();
  280. imx_gpcv2_init();
  281. return 0;
  282. }
  283. #else
  284. int arch_cpu_init(void)
  285. {
  286. init_cpu_basic();
  287. return 0;
  288. }
  289. #endif
  290. #ifdef CONFIG_ARCH_MISC_INIT
  291. int arch_misc_init(void)
  292. {
  293. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  294. if (is_mx7d())
  295. env_set("soc", "imx7d");
  296. else
  297. env_set("soc", "imx7s");
  298. #endif
  299. #ifdef CONFIG_FSL_CAAM
  300. sec_init();
  301. #endif
  302. return 0;
  303. }
  304. #endif
  305. #ifdef CONFIG_SERIAL_TAG
  306. /*
  307. * OCOTP_TESTER
  308. * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
  309. * OCOTP_TESTER describes a unique ID based on silicon wafer
  310. * and die X/Y position
  311. *
  312. * OCOTOP_TESTER offset 0x410
  313. * 31:0 fuse 0
  314. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  315. *
  316. * OCOTP_TESTER1 offset 0x420
  317. * 31:24 fuse 1
  318. * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  319. * 23:16 fuse 1
  320. * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
  321. * 15:11 fuse 1
  322. * The wafer number of the wafer on which the device was fabricated/SJC
  323. * CHALLENGE/ Unique ID
  324. * 10:0 fuse 1
  325. * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
  326. */
  327. void get_board_serial(struct tag_serialnr *serialnr)
  328. {
  329. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  330. struct fuse_bank *bank = &ocotp->bank[0];
  331. struct fuse_bank0_regs *fuse =
  332. (struct fuse_bank0_regs *)bank->fuse_regs;
  333. serialnr->low = fuse->tester0;
  334. serialnr->high = fuse->tester1;
  335. }
  336. #endif
  337. void set_wdog_reset(struct wdog_regs *wdog)
  338. {
  339. u32 reg = readw(&wdog->wcr);
  340. /*
  341. * Output WDOG_B signal to reset external pmic or POR_B decided by
  342. * the board desgin. Without external reset, the peripherals/DDR/
  343. * PMIC are not reset, that may cause system working abnormal.
  344. */
  345. reg = readw(&wdog->wcr);
  346. reg |= 1 << 3;
  347. /*
  348. * WDZST bit is write-once only bit. Align this bit in kernel,
  349. * otherwise kernel code will have no chance to set this bit.
  350. */
  351. reg |= 1 << 0;
  352. writew(reg, &wdog->wcr);
  353. }
  354. void s_init(void)
  355. {
  356. /* clock configuration. */
  357. clock_init();
  358. return;
  359. }
  360. #ifndef CONFIG_SPL_BUILD
  361. const struct boot_mode soc_boot_modes[] = {
  362. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  363. {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
  364. {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
  365. {NULL, 0},
  366. };
  367. int boot_mode_getprisec(void)
  368. {
  369. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  370. return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
  371. }
  372. #endif
  373. void reset_misc(void)
  374. {
  375. #ifndef CONFIG_SPL_BUILD
  376. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  377. lcdif_power_down();
  378. #endif
  379. #endif
  380. }