soc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <linux/delay.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/bootm.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/dma.h>
  19. #include <asm/mach-imx/hab.h>
  20. #include <stdbool.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <dm.h>
  24. #include <fsl_sec.h>
  25. #include <imx_thermal.h>
  26. #include <mmc.h>
  27. #define has_err007805() \
  28. (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
  29. struct scu_regs {
  30. u32 ctrl;
  31. u32 config;
  32. u32 status;
  33. u32 invalidate;
  34. u32 fpga_rev;
  35. };
  36. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL)
  37. static const struct imx_thermal_plat imx6_thermal_plat = {
  38. .regs = (void *)ANATOP_BASE_ADDR,
  39. .fuse_bank = 1,
  40. .fuse_word = 6,
  41. };
  42. U_BOOT_DEVICE(imx6_thermal) = {
  43. .name = "imx_thermal",
  44. .plat = &imx6_thermal_plat,
  45. };
  46. #endif
  47. #if defined(CONFIG_IMX_HAB)
  48. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  49. .bank = 0,
  50. .word = 6,
  51. };
  52. #endif
  53. u32 get_nr_cpus(void)
  54. {
  55. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  56. return readl(&scu->config) & 3;
  57. }
  58. u32 get_cpu_rev(void)
  59. {
  60. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  61. u32 reg = readl(&anatop->digprog_sololite);
  62. u32 type = ((reg >> 16) & 0xff);
  63. u32 major, cfg = 0;
  64. if (type != MXC_CPU_MX6SL) {
  65. reg = readl(&anatop->digprog);
  66. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  67. cfg = readl(&scu->config) & 3;
  68. type = ((reg >> 16) & 0xff);
  69. if (type == MXC_CPU_MX6DL) {
  70. if (!cfg)
  71. type = MXC_CPU_MX6SOLO;
  72. }
  73. if (type == MXC_CPU_MX6Q) {
  74. if (cfg == 1)
  75. type = MXC_CPU_MX6D;
  76. }
  77. if (type == MXC_CPU_MX6ULL) {
  78. if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
  79. type = MXC_CPU_MX6ULZ;
  80. }
  81. }
  82. major = ((reg >> 8) & 0xff);
  83. if ((major >= 1) &&
  84. ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
  85. major--;
  86. type = MXC_CPU_MX6QP;
  87. if (cfg == 1)
  88. type = MXC_CPU_MX6DP;
  89. }
  90. reg &= 0xff; /* mx6 silicon revision */
  91. /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
  92. if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
  93. reg = 0x3;
  94. return (type << 12) | (reg + (0x10 * (major + 1)));
  95. }
  96. /*
  97. * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
  98. * defines a 2-bit SPEED_GRADING
  99. */
  100. #define OCOTP_CFG3_SPEED_SHIFT 16
  101. #define OCOTP_CFG3_SPEED_800MHZ 0
  102. #define OCOTP_CFG3_SPEED_850MHZ 1
  103. #define OCOTP_CFG3_SPEED_1GHZ 2
  104. #define OCOTP_CFG3_SPEED_1P2GHZ 3
  105. /*
  106. * For i.MX6UL
  107. */
  108. #define OCOTP_CFG3_SPEED_528MHZ 1
  109. #define OCOTP_CFG3_SPEED_696MHZ 2
  110. /*
  111. * For i.MX6ULL
  112. */
  113. #define OCOTP_CFG3_SPEED_792MHZ 2
  114. #define OCOTP_CFG3_SPEED_900MHZ 3
  115. u32 get_cpu_speed_grade_hz(void)
  116. {
  117. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  118. struct fuse_bank *bank = &ocotp->bank[0];
  119. struct fuse_bank0_regs *fuse =
  120. (struct fuse_bank0_regs *)bank->fuse_regs;
  121. uint32_t val;
  122. val = readl(&fuse->cfg3);
  123. val >>= OCOTP_CFG3_SPEED_SHIFT;
  124. val &= 0x3;
  125. if (is_mx6ul()) {
  126. if (val == OCOTP_CFG3_SPEED_528MHZ)
  127. return 528000000;
  128. else if (val == OCOTP_CFG3_SPEED_696MHZ)
  129. return 696000000;
  130. else
  131. return 0;
  132. }
  133. if (is_mx6ull()) {
  134. if (val == OCOTP_CFG3_SPEED_528MHZ)
  135. return 528000000;
  136. else if (val == OCOTP_CFG3_SPEED_792MHZ)
  137. return 792000000;
  138. else if (val == OCOTP_CFG3_SPEED_900MHZ)
  139. return 900000000;
  140. else
  141. return 0;
  142. }
  143. switch (val) {
  144. /* Valid for IMX6DQ */
  145. case OCOTP_CFG3_SPEED_1P2GHZ:
  146. if (is_mx6dq() || is_mx6dqp())
  147. return 1200000000;
  148. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  149. case OCOTP_CFG3_SPEED_1GHZ:
  150. return 996000000;
  151. /* Valid for IMX6DQ */
  152. case OCOTP_CFG3_SPEED_850MHZ:
  153. if (is_mx6dq() || is_mx6dqp())
  154. return 852000000;
  155. /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
  156. case OCOTP_CFG3_SPEED_800MHZ:
  157. return 792000000;
  158. }
  159. return 0;
  160. }
  161. /*
  162. * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
  163. * defines a 2-bit Temperature Grade
  164. *
  165. * return temperature grade and min/max temperature in Celsius
  166. */
  167. #define OCOTP_MEM0_TEMP_SHIFT 6
  168. u32 get_cpu_temp_grade(int *minc, int *maxc)
  169. {
  170. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  171. struct fuse_bank *bank = &ocotp->bank[1];
  172. struct fuse_bank1_regs *fuse =
  173. (struct fuse_bank1_regs *)bank->fuse_regs;
  174. uint32_t val;
  175. val = readl(&fuse->mem0);
  176. val >>= OCOTP_MEM0_TEMP_SHIFT;
  177. val &= 0x3;
  178. if (minc && maxc) {
  179. if (val == TEMP_AUTOMOTIVE) {
  180. *minc = -40;
  181. *maxc = 125;
  182. } else if (val == TEMP_INDUSTRIAL) {
  183. *minc = -40;
  184. *maxc = 105;
  185. } else if (val == TEMP_EXTCOMMERCIAL) {
  186. *minc = -20;
  187. *maxc = 105;
  188. } else {
  189. *minc = 0;
  190. *maxc = 95;
  191. }
  192. }
  193. return val;
  194. }
  195. #ifdef CONFIG_REVISION_TAG
  196. u32 __weak get_board_rev(void)
  197. {
  198. u32 cpurev = get_cpu_rev();
  199. u32 type = ((cpurev >> 12) & 0xff);
  200. if (type == MXC_CPU_MX6SOLO)
  201. cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
  202. if (type == MXC_CPU_MX6D)
  203. cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
  204. return cpurev;
  205. }
  206. #endif
  207. static void clear_ldo_ramp(void)
  208. {
  209. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  210. int reg;
  211. /* ROM may modify LDO ramp up time according to fuse setting, so in
  212. * order to be in the safe side we neeed to reset these settings to
  213. * match the reset value: 0'b00
  214. */
  215. reg = readl(&anatop->ana_misc2);
  216. reg &= ~(0x3f << 24);
  217. writel(reg, &anatop->ana_misc2);
  218. }
  219. /*
  220. * Set the PMU_REG_CORE register
  221. *
  222. * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
  223. * Possible values are from 0.725V to 1.450V in steps of
  224. * 0.025V (25mV).
  225. */
  226. int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
  227. {
  228. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  229. u32 val, step, old, reg = readl(&anatop->reg_core);
  230. u8 shift;
  231. /* No LDO_SOC/PU/ARM */
  232. if (is_mx6sll())
  233. return 0;
  234. if (mv < 725)
  235. val = 0x00; /* Power gated off */
  236. else if (mv > 1450)
  237. val = 0x1F; /* Power FET switched full on. No regulation */
  238. else
  239. val = (mv - 700) / 25;
  240. clear_ldo_ramp();
  241. switch (ldo) {
  242. case LDO_SOC:
  243. shift = 18;
  244. break;
  245. case LDO_PU:
  246. shift = 9;
  247. break;
  248. case LDO_ARM:
  249. shift = 0;
  250. break;
  251. default:
  252. return -EINVAL;
  253. }
  254. old = (reg & (0x1F << shift)) >> shift;
  255. step = abs(val - old);
  256. if (step == 0)
  257. return 0;
  258. reg = (reg & ~(0x1F << shift)) | (val << shift);
  259. writel(reg, &anatop->reg_core);
  260. /*
  261. * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
  262. * step
  263. */
  264. udelay(3 * step);
  265. return 0;
  266. }
  267. static void set_ahb_rate(u32 val)
  268. {
  269. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  270. u32 reg, div;
  271. div = get_periph_clk() / val - 1;
  272. reg = readl(&mxc_ccm->cbcdr);
  273. writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
  274. (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
  275. }
  276. static void clear_mmdc_ch_mask(void)
  277. {
  278. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  279. u32 reg;
  280. reg = readl(&mxc_ccm->ccdr);
  281. /* Clear MMDC channel mask */
  282. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
  283. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
  284. else
  285. reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
  286. writel(reg, &mxc_ccm->ccdr);
  287. }
  288. #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
  289. static void init_bandgap(void)
  290. {
  291. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  292. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  293. struct fuse_bank *bank = &ocotp->bank[1];
  294. struct fuse_bank1_regs *fuse =
  295. (struct fuse_bank1_regs *)bank->fuse_regs;
  296. uint32_t val;
  297. /*
  298. * Ensure the bandgap has stabilized.
  299. */
  300. while (!(readl(&anatop->ana_misc0) & 0x80))
  301. ;
  302. /*
  303. * For best noise performance of the analog blocks using the
  304. * outputs of the bandgap, the reftop_selfbiasoff bit should
  305. * be set.
  306. */
  307. writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
  308. /*
  309. * On i.MX6ULL,we need to set VBGADJ bits according to the
  310. * REFTOP_TRIM[3:0] in fuse table
  311. * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  312. * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  313. * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  314. * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  315. * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  316. * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  317. * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  318. * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
  319. */
  320. if (is_mx6ull()) {
  321. val = readl(&fuse->mem0);
  322. val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  323. val &= 0x7;
  324. writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  325. &anatop->ana_misc0_set);
  326. }
  327. }
  328. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  329. static void noc_setup(void)
  330. {
  331. enable_ipu_clock();
  332. writel(0x80000201, 0xbb0608);
  333. /* Bypass IPU1 QoS generator */
  334. writel(0x00000002, 0x00bb048c);
  335. /* Bypass IPU2 QoS generator */
  336. writel(0x00000002, 0x00bb050c);
  337. /* Bandwidth THR for of PRE0 */
  338. writel(0x00000200, 0x00bb0690);
  339. /* Bandwidth THR for of PRE1 */
  340. writel(0x00000200, 0x00bb0710);
  341. /* Bandwidth THR for of PRE2 */
  342. writel(0x00000200, 0x00bb0790);
  343. /* Bandwidth THR for of PRE3 */
  344. writel(0x00000200, 0x00bb0810);
  345. /* Saturation THR for of PRE0 */
  346. writel(0x00000010, 0x00bb0694);
  347. /* Saturation THR for of PRE1 */
  348. writel(0x00000010, 0x00bb0714);
  349. /* Saturation THR for of PRE2 */
  350. writel(0x00000010, 0x00bb0794);
  351. /* Saturation THR for of PRE */
  352. writel(0x00000010, 0x00bb0814);
  353. disable_ipu_clock();
  354. }
  355. #endif
  356. int arch_cpu_init(void)
  357. {
  358. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  359. init_aips();
  360. /* Need to clear MMDC_CHx_MASK to make warm reset work. */
  361. clear_mmdc_ch_mask();
  362. /*
  363. * Disable self-bias circuit in the analog bandap.
  364. * The self-bias circuit is used by the bandgap during startup.
  365. * This bit should be set after the bandgap has initialized.
  366. */
  367. init_bandgap();
  368. if (!is_mx6ul() && !is_mx6ull()) {
  369. /*
  370. * When low freq boot is enabled, ROM will not set AHB
  371. * freq, so we need to ensure AHB freq is 132MHz in such
  372. * scenario.
  373. *
  374. * To i.MX6UL, when power up, default ARM core and
  375. * AHB rate is 396M and 132M.
  376. */
  377. if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
  378. set_ahb_rate(132000000);
  379. }
  380. if (is_mx6ul()) {
  381. if (is_soc_rev(CHIP_REV_1_0) == 0) {
  382. /*
  383. * According to the design team's requirement on
  384. * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
  385. * as open drain 100K (0x0000b8a0).
  386. * Only exists on TO1.0
  387. */
  388. writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
  389. } else {
  390. /*
  391. * From TO1.1, SNVS adds internal pull up control
  392. * for POR_B, the register filed is GPBIT[1:0],
  393. * after system boot up, it can be set to 2b'01
  394. * to disable internal pull up.It can save about
  395. * 30uA power in SNVS mode.
  396. */
  397. writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
  398. (~0x1400)) | 0x400,
  399. MX6UL_SNVS_LP_BASE_ADDR + 0x10);
  400. }
  401. }
  402. if (is_mx6ull()) {
  403. /*
  404. * GPBIT[1:0] is suggested to set to 2'b11:
  405. * 2'b00 : always PUP100K
  406. * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
  407. * 2'b10 : always disable PUP100K
  408. * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
  409. * register offset is different from i.MX6UL, since
  410. * i.MX6UL is fixed by ECO.
  411. */
  412. writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
  413. 0x3, MX6UL_SNVS_LP_BASE_ADDR);
  414. }
  415. /* Set perclk to source from OSC 24MHz */
  416. if (has_err007805())
  417. setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
  418. imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
  419. if (is_mx6sx())
  420. setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
  421. init_src();
  422. #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
  423. if (is_mx6dqp())
  424. noc_setup();
  425. #endif
  426. return 0;
  427. }
  428. #ifdef CONFIG_ENV_IS_IN_MMC
  429. __weak int board_mmc_get_env_dev(int devno)
  430. {
  431. return CONFIG_SYS_MMC_ENV_DEV;
  432. }
  433. static int mmc_get_boot_dev(void)
  434. {
  435. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  436. u32 soc_sbmr = readl(&src_regs->sbmr1);
  437. u32 bootsel;
  438. int devno;
  439. /*
  440. * Refer to
  441. * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
  442. * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
  443. * i.MX6SL/SX/UL has same layout.
  444. */
  445. bootsel = (soc_sbmr & 0x000000FF) >> 6;
  446. /* No boot from sd/mmc */
  447. if (bootsel != 1)
  448. return -1;
  449. /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  450. devno = (soc_sbmr & 0x00001800) >> 11;
  451. return devno;
  452. }
  453. int mmc_get_env_dev(void)
  454. {
  455. int devno = mmc_get_boot_dev();
  456. /* If not boot from sd/mmc, use default value */
  457. if (devno < 0)
  458. return CONFIG_SYS_MMC_ENV_DEV;
  459. return board_mmc_get_env_dev(devno);
  460. }
  461. #ifdef CONFIG_SYS_MMC_ENV_PART
  462. __weak int board_mmc_get_env_part(int devno)
  463. {
  464. return CONFIG_SYS_MMC_ENV_PART;
  465. }
  466. uint mmc_get_env_part(struct mmc *mmc)
  467. {
  468. int devno = mmc_get_boot_dev();
  469. /* If not boot from sd/mmc, use default value */
  470. if (devno < 0)
  471. return CONFIG_SYS_MMC_ENV_PART;
  472. return board_mmc_get_env_part(devno);
  473. }
  474. #endif
  475. #endif
  476. int board_postclk_init(void)
  477. {
  478. /* NO LDO SOC on i.MX6SLL */
  479. if (is_mx6sll())
  480. return 0;
  481. set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
  482. return 0;
  483. }
  484. #ifndef CONFIG_SPL_BUILD
  485. /*
  486. * cfg_val will be used for
  487. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  488. * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
  489. * instead of SBMR1 to determine the boot device.
  490. */
  491. const struct boot_mode soc_boot_modes[] = {
  492. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  493. /* reserved value should start rom usb */
  494. #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
  495. {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  496. #else
  497. {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  498. #endif
  499. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  500. {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  501. {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  502. {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  503. {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  504. /* 4 bit bus width */
  505. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  506. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  507. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  508. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  509. {NULL, 0},
  510. };
  511. #endif
  512. void reset_misc(void)
  513. {
  514. #ifndef CONFIG_SPL_BUILD
  515. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  516. lcdif_power_down();
  517. #endif
  518. #endif
  519. }
  520. void s_init(void)
  521. {
  522. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  523. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  524. u32 mask480;
  525. u32 mask528;
  526. u32 reg, periph1, periph2;
  527. if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
  528. return;
  529. /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
  530. * to make sure PFD is working right, otherwise, PFDs may
  531. * not output clock after reset, MX6DL and MX6SL have added 396M pfd
  532. * workaround in ROM code, as bus clock need it
  533. */
  534. mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
  535. ANATOP_PFD_CLKGATE_MASK(1) |
  536. ANATOP_PFD_CLKGATE_MASK(2) |
  537. ANATOP_PFD_CLKGATE_MASK(3);
  538. mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
  539. ANATOP_PFD_CLKGATE_MASK(3);
  540. reg = readl(&ccm->cbcmr);
  541. periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
  542. >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
  543. periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
  544. >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
  545. /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
  546. if ((periph2 != 0x2) && (periph1 != 0x2))
  547. mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
  548. if ((periph2 != 0x1) && (periph1 != 0x1) &&
  549. (periph2 != 0x3) && (periph1 != 0x3))
  550. mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
  551. writel(mask480, &anatop->pfd_480_set);
  552. writel(mask528, &anatop->pfd_528_set);
  553. writel(mask480, &anatop->pfd_480_clr);
  554. writel(mask528, &anatop->pfd_528_clr);
  555. }
  556. #ifdef CONFIG_IMX_HDMI
  557. void imx_enable_hdmi_phy(void)
  558. {
  559. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  560. u8 reg;
  561. reg = readb(&hdmi->phy_conf0);
  562. reg |= HDMI_PHY_CONF0_PDZ_MASK;
  563. writeb(reg, &hdmi->phy_conf0);
  564. udelay(3000);
  565. reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
  566. writeb(reg, &hdmi->phy_conf0);
  567. udelay(3000);
  568. reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
  569. writeb(reg, &hdmi->phy_conf0);
  570. writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
  571. }
  572. void imx_setup_hdmi(void)
  573. {
  574. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  575. struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
  576. int reg, count;
  577. u8 val;
  578. /* Turn on HDMI PHY clock */
  579. reg = readl(&mxc_ccm->CCGR2);
  580. reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
  581. MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
  582. writel(reg, &mxc_ccm->CCGR2);
  583. writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
  584. reg = readl(&mxc_ccm->chsccdr);
  585. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
  586. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
  587. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  588. reg |= (CHSCCDR_PODF_DIVIDE_BY_3
  589. << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
  590. |(CHSCCDR_IPU_PRE_CLK_540M_PFD
  591. << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
  592. writel(reg, &mxc_ccm->chsccdr);
  593. /* Clear the overflow condition */
  594. if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
  595. /* TMDS software reset */
  596. writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
  597. val = readb(&hdmi->fc_invidconf);
  598. /* Need minimum 3 times to write to clear the register */
  599. for (count = 0 ; count < 5 ; count++)
  600. writeb(val, &hdmi->fc_invidconf);
  601. }
  602. }
  603. #endif
  604. #ifdef CONFIG_ARCH_MISC_INIT
  605. int arch_misc_init(void)
  606. {
  607. #ifdef CONFIG_FSL_CAAM
  608. sec_init();
  609. #endif
  610. return 0;
  611. }
  612. #endif
  613. /*
  614. * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
  615. * MX6Q and MX6QP processors
  616. */
  617. void gpr_init(void)
  618. {
  619. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  620. /*
  621. * If this function is used in a common MX6 spl implementation
  622. * we have to ensure that it is only called for suitable cpu types,
  623. * otherwise it breaks hardware parts like enet1, can1, can2, etc.
  624. */
  625. if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
  626. return;
  627. /* enable AXI cache for VDOA/VPU/IPU */
  628. writel(0xF00000CF, &iomux->gpr[4]);
  629. if (is_mx6dqp()) {
  630. /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
  631. writel(0x77177717, &iomux->gpr[6]);
  632. writel(0x77177717, &iomux->gpr[7]);
  633. } else {
  634. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  635. writel(0x007F007F, &iomux->gpr[6]);
  636. writel(0x007F007F, &iomux->gpr[7]);
  637. }
  638. }