openpiton-riscv64.dts 3.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
  3. /*
  4. * This dts is for a dual core instance of OpenPiton+Ariane built
  5. * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
  6. * are automatically generated by the OpenPiton build system and
  7. * this configuration may not be what you need if your configuration
  8. * is different from the below.
  9. */
  10. /dts-v1/;
  11. / {
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. compatible = "openpiton,riscv64";
  15. chosen {
  16. stdout-path = "uart0:115200";
  17. };
  18. aliases {
  19. console = &uart0;
  20. serial0 = &uart0;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. timebase-frequency = <520835>;
  26. CPU0: cpu@0 {
  27. clocks = <&clk0>;
  28. u-boot,dm-spl;
  29. device_type = "cpu";
  30. reg = <0>;
  31. compatible = "openhwgroup,cva6", "riscv";
  32. riscv,isa = "rv64imafdc";
  33. mmu-type = "riscv,sv39";
  34. tlb-split;
  35. // HLIC - hart local interrupt controller
  36. CPU0_intc: interrupt-controller {
  37. #interrupt-cells = <1>;
  38. interrupt-controller;
  39. compatible = "riscv,cpu-intc";
  40. };
  41. };
  42. CPU1: cpu@1 {
  43. clocks = <&clk0>;
  44. device_type = "cpu";
  45. reg = <1>;
  46. compatible = "openhwgroup,cva6", "riscv";
  47. riscv,isa = "rv64imafdc";
  48. mmu-type = "riscv,sv39";
  49. tlb-split;
  50. // HLIC - hart local interrupt controller
  51. CPU1_intc: interrupt-controller {
  52. #interrupt-cells = <1>;
  53. interrupt-controller;
  54. compatible = "riscv,cpu-intc";
  55. };
  56. };
  57. };
  58. clocks {
  59. clk0: osc {
  60. compatible = "fixed-clock";
  61. #clock-cells = <0>;
  62. clock-frequency = <66667000>;
  63. };
  64. };
  65. memory@80000000 {
  66. u-boot,dm-spl;
  67. device_type = "memory";
  68. reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
  69. };
  70. soc {
  71. #address-cells = <2>;
  72. #size-cells = <2>;
  73. compatible = "openpiton,chipset", "simple-bus";
  74. ranges;
  75. uart0: uart@fff0c2c000 {
  76. compatible = "ns16550", "openpiton,ns16550";
  77. reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
  78. interrupt-parent = <&PLIC0>;
  79. interrupts = <1>;
  80. reg-shift = <0>;
  81. // regs are spaced on 8 bit boundary
  82. };
  83. eth: ethernet@fff0d00000 {
  84. compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
  85. device_type = "network";
  86. reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
  87. interrupt-parent = <&PLIC0>;
  88. interrupts = <2>;
  89. phy-handle = <&phy0>;
  90. xlnx,duplex = <0x1>;
  91. xlnx,include-global-buffers = <0x1>;
  92. xlnx,include-internal-loopback = <0x0>;
  93. xlnx,include-mdio = <0x1>;
  94. xlnx,rx-ping-pong = <0x1>;
  95. xlnx,s-axi-id-width = <0x1>;
  96. xlnx,tx-ping-pong = <0x1>;
  97. xlnx,use-internal = <0x0>;
  98. axi_ethernetlite_0_mdio: mdio {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. phy0: phy@1 {
  102. compatible = "ethernet-phy-id001C.C915";
  103. device_type = "ethernet-phy";
  104. reg = <1>;
  105. };
  106. };
  107. };
  108. sdhci_0: sdhci@f000000000 {
  109. u-boot,dm-spl;
  110. compatible = "openpiton,piton-mmc", "openpiton,mmc";
  111. reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
  112. };
  113. clint@fff1020000 {
  114. compatible = "sifive,clint0", "openpiton,clint";
  115. interrupts-extended = < &CPU0_intc 3
  116. &CPU0_intc 7
  117. &CPU1_intc 3
  118. &CPU1_intc 7 >;
  119. reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
  120. clocks = <&clk0>;
  121. };
  122. PLIC0: plic@fff1100000 {
  123. u-boot,dm-spl;
  124. #interrupt-cells = <1>;
  125. compatible = "sifive,plic-1.0.0", "openpiton,plic";
  126. interrupt-controller;
  127. interrupts-extended = < &CPU0_intc 11
  128. &CPU0_intc 9
  129. &CPU1_intc 11
  130. &CPU1_intc 9 >;
  131. reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
  132. riscv,max-priority = <7>;
  133. riscv,ndev = <2>;
  134. };
  135. };
  136. };