encoding.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2017 Microsemi Corporation.
  4. * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
  5. */
  6. #ifndef RISCV_CSR_ENCODING_H
  7. #define RISCV_CSR_ENCODING_H
  8. #include <asm/csr.h>
  9. #ifndef __ASSEMBLY__
  10. #include <linux/bitops.h>
  11. #endif
  12. #if CONFIG_IS_ENABLED(RISCV_SMODE)
  13. #define MODE_PREFIX(__suffix) s##__suffix
  14. #else
  15. #define MODE_PREFIX(__suffix) m##__suffix
  16. #endif
  17. #define MSTATUS_UIE 0x00000001
  18. #define MSTATUS_SIE 0x00000002
  19. #define MSTATUS_HIE 0x00000004
  20. #define MSTATUS_MIE 0x00000008
  21. #define MSTATUS_UPIE 0x00000010
  22. #define MSTATUS_SPIE 0x00000020
  23. #define MSTATUS_HPIE 0x00000040
  24. #define MSTATUS_MPIE 0x00000080
  25. #define MSTATUS_SPP 0x00000100
  26. #define MSTATUS_HPP 0x00000600
  27. #define MSTATUS_MPP 0x00001800
  28. #define MSTATUS_FS 0x00006000
  29. #define MSTATUS_XS 0x00018000
  30. #define MSTATUS_MPRV 0x00020000
  31. #define MSTATUS_PUM 0x00040000
  32. #define MSTATUS_VM 0x1F000000
  33. #define MSTATUS32_SD 0x80000000
  34. #define MSTATUS64_SD 0x8000000000000000
  35. #define MCAUSE32_CAUSE 0x7FFFFFFF
  36. #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
  37. #define MCAUSE32_INT 0x80000000
  38. #define MCAUSE64_INT 0x8000000000000000
  39. #define SSTATUS_UIE 0x00000001
  40. #define SSTATUS_SIE 0x00000002
  41. #define SSTATUS_UPIE 0x00000010
  42. #define SSTATUS_SPIE 0x00000020
  43. #define SSTATUS_SPP 0x00000100
  44. #define SSTATUS_FS 0x00006000
  45. #define SSTATUS_XS 0x00018000
  46. #define SSTATUS_PUM 0x00040000
  47. #define SSTATUS32_SD 0x80000000
  48. #define SSTATUS64_SD 0x8000000000000000
  49. #define MIP_SSIP BIT(IRQ_S_SOFT)
  50. #define MIP_MSIP BIT(IRQ_M_SOFT)
  51. #define MIP_STIP BIT(IRQ_S_TIMER)
  52. #define MIP_MTIP BIT(IRQ_M_TIMER)
  53. #define MIP_SEIP BIT(IRQ_S_EXT)
  54. #define MIP_MEIP BIT(IRQ_M_EXT)
  55. #define SIP_SSIP MIP_SSIP
  56. #define SIP_STIP MIP_STIP
  57. #define PRV_U 0
  58. #define PRV_S 1
  59. #define PRV_H 2
  60. #define PRV_M 3
  61. #define VM_MBARE 0
  62. #define VM_MBB 1
  63. #define VM_MBBID 2
  64. #define VM_SV32 8
  65. #define VM_SV39 9
  66. #define VM_SV48 10
  67. #define CAUSE_MISALIGNED_FETCH 0
  68. #define CAUSE_FETCH_ACCESS 1
  69. #define CAUSE_ILLEGAL_INSTRUCTION 2
  70. #define CAUSE_BREAKPOINT 3
  71. #define CAUSE_MISALIGNED_LOAD 4
  72. #define CAUSE_LOAD_ACCESS 5
  73. #define CAUSE_MISALIGNED_STORE 6
  74. #define CAUSE_STORE_ACCESS 7
  75. #define CAUSE_USER_ECALL 8
  76. #define CAUSE_SUPERVISOR_ECALL 9
  77. #define CAUSE_MACHINE_ECALL 11
  78. #define CAUSE_FETCH_PAGE_FAULT 12
  79. #define CAUSE_LOAD_PAGE_FAULT 13
  80. #define CAUSE_STORE_PAGE_FAULT 15
  81. #define DEFAULT_RSTVEC 0x00001000
  82. #define DEFAULT_NMIVEC 0x00001004
  83. #define DEFAULT_MTVEC 0x00001010
  84. #define CONFIG_STRING_ADDR 0x0000100C
  85. #define EXT_IO_BASE 0x40000000
  86. #define DRAM_BASE 0x80000000
  87. // page table entry (PTE) fields
  88. #define PTE_V 0x001 // Valid
  89. #define PTE_TYPE 0x01E // Type
  90. #define PTE_R 0x020 // Referenced
  91. #define PTE_D 0x040 // Dirty
  92. #define PTE_SOFT 0x380 // Reserved for Software
  93. #define PTE_TYPE_TABLE 0x00
  94. #define PTE_TYPE_TABLE_GLOBAL 0x02
  95. #define PTE_TYPE_URX_SR 0x04
  96. #define PTE_TYPE_URWX_SRW 0x06
  97. #define PTE_TYPE_UR_SR 0x08
  98. #define PTE_TYPE_URW_SRW 0x0A
  99. #define PTE_TYPE_URX_SRX 0x0C
  100. #define PTE_TYPE_URWX_SRWX0x0E
  101. #define PTE_TYPE_SR 0x10
  102. #define PTE_TYPE_SRW 0x12
  103. #define PTE_TYPE_SRX 0x14
  104. #define PTE_TYPE_SRWX 0x16
  105. #define PTE_TYPE_SR_GLOBAL 0x18
  106. #define PTE_TYPE_SRW_GLOBAL 0x1A
  107. #define PTE_TYPE_SRX_GLOBAL 0x1C
  108. #define PTE_TYPE_SRWX_GLOBAL 0x1E
  109. #define PTE_PPN_SHIFT 10
  110. #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
  111. #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
  112. #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
  113. #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
  114. #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
  115. #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
  116. #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
  117. #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
  118. typeof(_PTE) (PTE) = (_PTE); \
  119. typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
  120. ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
  121. (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
  122. ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
  123. #ifdef __riscv
  124. #ifdef CONFIG_64BIT
  125. # define MSTATUS_SD MSTATUS64_SD
  126. # define SSTATUS_SD SSTATUS64_SD
  127. # define MCAUSE_INT MCAUSE64_INT
  128. # define MCAUSE_CAUSE MCAUSE64_CAUSE
  129. # define RISCV_PGLEVEL_BITS 9
  130. #else
  131. # define MSTATUS_SD MSTATUS32_SD
  132. # define SSTATUS_SD SSTATUS32_SD
  133. # define RISCV_PGLEVEL_BITS 10
  134. # define MCAUSE_INT MCAUSE32_INT
  135. # define MCAUSE_CAUSE MCAUSE32_CAUSE
  136. #endif
  137. #define RISCV_PGSHIFT 12
  138. #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
  139. #endif /* __riscv */
  140. #endif /* RISCV_CSR_ENCODING_H */