board_f.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <bloblist.h>
  13. #include <clock_legacy.h>
  14. #include <console.h>
  15. #include <cpu.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <env.h>
  19. #include <env_internal.h>
  20. #include <fdtdec.h>
  21. #include <fs.h>
  22. #include <hang.h>
  23. #include <i2c.h>
  24. #include <init.h>
  25. #include <initcall.h>
  26. #include <lcd.h>
  27. #include <malloc.h>
  28. #include <mapmem.h>
  29. #include <os.h>
  30. #include <post.h>
  31. #include <relocate.h>
  32. #include <serial.h>
  33. #ifdef CONFIG_SPL
  34. #include <spl.h>
  35. #endif
  36. #include <status_led.h>
  37. #include <sysreset.h>
  38. #include <timer.h>
  39. #include <trace.h>
  40. #include <video.h>
  41. #include <watchdog.h>
  42. #ifdef CONFIG_MACH_TYPE
  43. #include <asm/mach-types.h>
  44. #endif
  45. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  46. #include <asm/mp.h>
  47. #endif
  48. #include <asm/io.h>
  49. #include <asm/sections.h>
  50. #include <dm/root.h>
  51. #include <linux/errno.h>
  52. /*
  53. * Pointer to initial global data area
  54. *
  55. * Here we initialize it if needed.
  56. */
  57. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  58. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  59. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  60. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  61. #else
  62. DECLARE_GLOBAL_DATA_PTR;
  63. #endif
  64. /*
  65. * TODO(sjg@chromium.org): IMO this code should be
  66. * refactored to a single function, something like:
  67. *
  68. * void led_set_state(enum led_colour_t colour, int on);
  69. */
  70. /************************************************************************
  71. * Coloured LED functionality
  72. ************************************************************************
  73. * May be supplied by boards if desired
  74. */
  75. __weak void coloured_LED_init(void) {}
  76. __weak void red_led_on(void) {}
  77. __weak void red_led_off(void) {}
  78. __weak void green_led_on(void) {}
  79. __weak void green_led_off(void) {}
  80. __weak void yellow_led_on(void) {}
  81. __weak void yellow_led_off(void) {}
  82. __weak void blue_led_on(void) {}
  83. __weak void blue_led_off(void) {}
  84. /*
  85. * Why is gd allocated a register? Prior to reloc it might be better to
  86. * just pass it around to each function in this file?
  87. *
  88. * After reloc one could argue that it is hardly used and doesn't need
  89. * to be in a register. Or if it is it should perhaps hold pointers to all
  90. * global data for all modules, so that post-reloc we can avoid the massive
  91. * literal pool we get on ARM. Or perhaps just encourage each module to use
  92. * a structure...
  93. */
  94. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  95. static int init_func_watchdog_init(void)
  96. {
  97. # if defined(CONFIG_HW_WATCHDOG) && \
  98. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  99. defined(CONFIG_SH) || \
  100. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  101. defined(CONFIG_IMX_WATCHDOG))
  102. hw_watchdog_init();
  103. puts(" Watchdog enabled\n");
  104. # endif
  105. WATCHDOG_RESET();
  106. return 0;
  107. }
  108. int init_func_watchdog_reset(void)
  109. {
  110. WATCHDOG_RESET();
  111. return 0;
  112. }
  113. #endif /* CONFIG_WATCHDOG */
  114. __weak void board_add_ram_info(int use_default)
  115. {
  116. /* please define platform specific board_add_ram_info() */
  117. }
  118. static int init_baud_rate(void)
  119. {
  120. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  121. return 0;
  122. }
  123. static int display_text_info(void)
  124. {
  125. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  126. ulong bss_start, bss_end, text_base;
  127. bss_start = (ulong)&__bss_start;
  128. bss_end = (ulong)&__bss_end;
  129. #ifdef CONFIG_SYS_TEXT_BASE
  130. text_base = CONFIG_SYS_TEXT_BASE;
  131. #else
  132. text_base = CONFIG_SYS_MONITOR_BASE;
  133. #endif
  134. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  135. text_base, bss_start, bss_end);
  136. #endif
  137. return 0;
  138. }
  139. #ifdef CONFIG_SYSRESET
  140. static int print_resetinfo(void)
  141. {
  142. struct udevice *dev;
  143. char status[256];
  144. int ret;
  145. ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
  146. if (ret) {
  147. debug("%s: No sysreset device found (error: %d)\n",
  148. __func__, ret);
  149. /* Not all boards have sysreset drivers available during early
  150. * boot, so don't fail if one can't be found.
  151. */
  152. return 0;
  153. }
  154. if (!sysreset_get_status(dev, status, sizeof(status)))
  155. printf("%s", status);
  156. return 0;
  157. }
  158. #endif
  159. #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
  160. static int print_cpuinfo(void)
  161. {
  162. struct udevice *dev;
  163. char desc[512];
  164. int ret;
  165. ret = uclass_first_device_err(UCLASS_CPU, &dev);
  166. if (ret) {
  167. debug("%s: Could not get CPU device (err = %d)\n",
  168. __func__, ret);
  169. return ret;
  170. }
  171. ret = cpu_get_desc(dev, desc, sizeof(desc));
  172. if (ret) {
  173. debug("%s: Could not get CPU description (err = %d)\n",
  174. dev->name, ret);
  175. return ret;
  176. }
  177. printf("CPU: %s\n", desc);
  178. return 0;
  179. }
  180. #endif
  181. static int announce_dram_init(void)
  182. {
  183. puts("DRAM: ");
  184. return 0;
  185. }
  186. static int show_dram_config(void)
  187. {
  188. unsigned long long size;
  189. #ifdef CONFIG_NR_DRAM_BANKS
  190. int i;
  191. debug("\nRAM Configuration:\n");
  192. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  193. size += gd->bd->bi_dram[i].size;
  194. debug("Bank #%d: %llx ", i,
  195. (unsigned long long)(gd->bd->bi_dram[i].start));
  196. #ifdef DEBUG
  197. print_size(gd->bd->bi_dram[i].size, "\n");
  198. #endif
  199. }
  200. debug("\nDRAM: ");
  201. #else
  202. size = gd->ram_size;
  203. #endif
  204. print_size(size, "");
  205. board_add_ram_info(0);
  206. putc('\n');
  207. return 0;
  208. }
  209. __weak int dram_init_banksize(void)
  210. {
  211. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  212. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  213. gd->bd->bi_dram[0].size = get_effective_memsize();
  214. #endif
  215. return 0;
  216. }
  217. #if defined(CONFIG_SYS_I2C)
  218. static int init_func_i2c(void)
  219. {
  220. puts("I2C: ");
  221. #ifdef CONFIG_SYS_I2C
  222. i2c_init_all();
  223. #else
  224. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  225. #endif
  226. puts("ready\n");
  227. return 0;
  228. }
  229. #endif
  230. #if defined(CONFIG_VID)
  231. __weak int init_func_vid(void)
  232. {
  233. return 0;
  234. }
  235. #endif
  236. static int setup_mon_len(void)
  237. {
  238. #if defined(__ARM__) || defined(__MICROBLAZE__)
  239. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  240. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  241. gd->mon_len = (ulong)&_end - (ulong)_init;
  242. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  243. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  244. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  245. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  246. #elif defined(CONFIG_SYS_MONITOR_BASE)
  247. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  248. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  249. #endif
  250. return 0;
  251. }
  252. static int setup_spl_handoff(void)
  253. {
  254. #if CONFIG_IS_ENABLED(HANDOFF)
  255. gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
  256. sizeof(struct spl_handoff));
  257. debug("Found SPL hand-off info %p\n", gd->spl_handoff);
  258. #endif
  259. return 0;
  260. }
  261. __weak int arch_cpu_init(void)
  262. {
  263. return 0;
  264. }
  265. __weak int mach_cpu_init(void)
  266. {
  267. return 0;
  268. }
  269. /* Get the top of usable RAM */
  270. __weak ulong board_get_usable_ram_top(ulong total_size)
  271. {
  272. #ifdef CONFIG_SYS_SDRAM_BASE
  273. /*
  274. * Detect whether we have so much RAM that it goes past the end of our
  275. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  276. */
  277. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  278. /*
  279. * Will wrap back to top of 32-bit space when reservations
  280. * are made.
  281. */
  282. return 0;
  283. #endif
  284. return gd->ram_top;
  285. }
  286. static int setup_dest_addr(void)
  287. {
  288. debug("Monitor len: %08lX\n", gd->mon_len);
  289. /*
  290. * Ram is setup, size stored in gd !!
  291. */
  292. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  293. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  294. /*
  295. * Subtract specified amount of memory to hide so that it won't
  296. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  297. * the Linux kernel should now get passed the now "corrected"
  298. * memory size and won't touch it either. This should work
  299. * for arch/ppc and arch/powerpc. Only Linux board ports in
  300. * arch/powerpc with bootwrapper support, that recalculate the
  301. * memory size from the SDRAM controller setup will have to
  302. * get fixed.
  303. */
  304. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  305. #endif
  306. #ifdef CONFIG_SYS_SDRAM_BASE
  307. gd->ram_base = CONFIG_SYS_SDRAM_BASE;
  308. #endif
  309. gd->ram_top = gd->ram_base + get_effective_memsize();
  310. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  311. gd->relocaddr = gd->ram_top;
  312. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  313. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  314. /*
  315. * We need to make sure the location we intend to put secondary core
  316. * boot code is reserved and not used by any part of u-boot
  317. */
  318. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  319. gd->relocaddr = determine_mp_bootpg(NULL);
  320. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  321. }
  322. #endif
  323. return 0;
  324. }
  325. #ifdef CONFIG_PRAM
  326. /* reserve protected RAM */
  327. static int reserve_pram(void)
  328. {
  329. ulong reg;
  330. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  331. gd->relocaddr -= (reg << 10); /* size is in kB */
  332. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  333. gd->relocaddr);
  334. return 0;
  335. }
  336. #endif /* CONFIG_PRAM */
  337. /* Round memory pointer down to next 4 kB limit */
  338. static int reserve_round_4k(void)
  339. {
  340. gd->relocaddr &= ~(4096 - 1);
  341. return 0;
  342. }
  343. #ifdef CONFIG_ARM
  344. __weak int reserve_mmu(void)
  345. {
  346. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  347. /* reserve TLB table */
  348. gd->arch.tlb_size = PGTABLE_SIZE;
  349. gd->relocaddr -= gd->arch.tlb_size;
  350. /* round down to next 64 kB limit */
  351. gd->relocaddr &= ~(0x10000 - 1);
  352. gd->arch.tlb_addr = gd->relocaddr;
  353. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  354. gd->arch.tlb_addr + gd->arch.tlb_size);
  355. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  356. /*
  357. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  358. * with location within secure ram.
  359. */
  360. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  361. #endif
  362. #endif
  363. return 0;
  364. }
  365. #endif
  366. static int reserve_video(void)
  367. {
  368. #ifdef CONFIG_DM_VIDEO
  369. ulong addr;
  370. int ret;
  371. addr = gd->relocaddr;
  372. ret = video_reserve(&addr);
  373. if (ret)
  374. return ret;
  375. gd->relocaddr = addr;
  376. #elif defined(CONFIG_LCD)
  377. # ifdef CONFIG_FB_ADDR
  378. gd->fb_base = CONFIG_FB_ADDR;
  379. # else
  380. /* reserve memory for LCD display (always full pages) */
  381. gd->relocaddr = lcd_setmem(gd->relocaddr);
  382. gd->fb_base = gd->relocaddr;
  383. # endif /* CONFIG_FB_ADDR */
  384. #endif
  385. return 0;
  386. }
  387. static int reserve_trace(void)
  388. {
  389. #ifdef CONFIG_TRACE
  390. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  391. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  392. debug("Reserving %luk for trace data at: %08lx\n",
  393. (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  394. #endif
  395. return 0;
  396. }
  397. static int reserve_uboot(void)
  398. {
  399. if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
  400. /*
  401. * reserve memory for U-Boot code, data & bss
  402. * round down to next 4 kB limit
  403. */
  404. gd->relocaddr -= gd->mon_len;
  405. gd->relocaddr &= ~(4096 - 1);
  406. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  407. /* round down to next 64 kB limit so that IVPR stays aligned */
  408. gd->relocaddr &= ~(65536 - 1);
  409. #endif
  410. debug("Reserving %ldk for U-Boot at: %08lx\n",
  411. gd->mon_len >> 10, gd->relocaddr);
  412. }
  413. gd->start_addr_sp = gd->relocaddr;
  414. return 0;
  415. }
  416. /*
  417. * reserve after start_addr_sp the requested size and make the stack pointer
  418. * 16-byte aligned, this alignment is needed for cast on the reserved memory
  419. * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
  420. * = ARMv8 Instruction Set Overview: quad word, 16 bytes
  421. */
  422. static unsigned long reserve_stack_aligned(size_t size)
  423. {
  424. return ALIGN_DOWN(gd->start_addr_sp - size, 16);
  425. }
  426. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  427. static int reserve_noncached(void)
  428. {
  429. /*
  430. * The value of gd->start_addr_sp must match the value of malloc_start
  431. * calculated in boatrd_f.c:initr_malloc(), which is passed to
  432. * board_r.c:mem_malloc_init() and then used by
  433. * cache.c:noncached_init()
  434. *
  435. * These calculations must match the code in cache.c:noncached_init()
  436. */
  437. gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
  438. MMU_SECTION_SIZE;
  439. gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
  440. MMU_SECTION_SIZE);
  441. debug("Reserving %dM for noncached_alloc() at: %08lx\n",
  442. CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
  443. return 0;
  444. }
  445. #endif
  446. /* reserve memory for malloc() area */
  447. static int reserve_malloc(void)
  448. {
  449. gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
  450. debug("Reserving %dk for malloc() at: %08lx\n",
  451. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  452. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  453. reserve_noncached();
  454. #endif
  455. return 0;
  456. }
  457. /* (permanently) allocate a Board Info struct */
  458. static int reserve_board(void)
  459. {
  460. if (!gd->bd) {
  461. gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t));
  462. gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
  463. memset(gd->bd, '\0', sizeof(bd_t));
  464. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  465. sizeof(bd_t), gd->start_addr_sp);
  466. }
  467. return 0;
  468. }
  469. static int setup_machine(void)
  470. {
  471. #ifdef CONFIG_MACH_TYPE
  472. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  473. #endif
  474. return 0;
  475. }
  476. static int reserve_global_data(void)
  477. {
  478. gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
  479. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  480. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  481. sizeof(gd_t), gd->start_addr_sp);
  482. return 0;
  483. }
  484. static int reserve_fdt(void)
  485. {
  486. #ifndef CONFIG_OF_EMBED
  487. /*
  488. * If the device tree is sitting immediately above our image then we
  489. * must relocate it. If it is embedded in the data section, then it
  490. * will be relocated with other data.
  491. */
  492. if (gd->fdt_blob) {
  493. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
  494. gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
  495. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  496. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  497. gd->fdt_size, gd->start_addr_sp);
  498. }
  499. #endif
  500. return 0;
  501. }
  502. static int reserve_bootstage(void)
  503. {
  504. #ifdef CONFIG_BOOTSTAGE
  505. int size = bootstage_get_size();
  506. gd->start_addr_sp = reserve_stack_aligned(size);
  507. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  508. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  509. gd->start_addr_sp);
  510. #endif
  511. return 0;
  512. }
  513. __weak int arch_reserve_stacks(void)
  514. {
  515. return 0;
  516. }
  517. static int reserve_stacks(void)
  518. {
  519. /* make stack pointer 16-byte aligned */
  520. gd->start_addr_sp = reserve_stack_aligned(16);
  521. /*
  522. * let the architecture-specific code tailor gd->start_addr_sp and
  523. * gd->irq_sp
  524. */
  525. return arch_reserve_stacks();
  526. }
  527. static int reserve_bloblist(void)
  528. {
  529. #ifdef CONFIG_BLOBLIST
  530. gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE);
  531. gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
  532. #endif
  533. return 0;
  534. }
  535. static int display_new_sp(void)
  536. {
  537. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  538. return 0;
  539. }
  540. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  541. defined(CONFIG_SH)
  542. static int setup_board_part1(void)
  543. {
  544. bd_t *bd = gd->bd;
  545. /*
  546. * Save local variables to board info struct
  547. */
  548. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  549. bd->bi_memsize = gd->ram_size; /* size in bytes */
  550. #ifdef CONFIG_SYS_SRAM_BASE
  551. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  552. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  553. #endif
  554. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  555. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  556. #endif
  557. #if defined(CONFIG_M68K)
  558. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  559. #endif
  560. #if defined(CONFIG_MPC83xx)
  561. bd->bi_immrbar = CONFIG_SYS_IMMR;
  562. #endif
  563. return 0;
  564. }
  565. #endif
  566. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  567. static int setup_board_part2(void)
  568. {
  569. bd_t *bd = gd->bd;
  570. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  571. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  572. #if defined(CONFIG_CPM2)
  573. bd->bi_cpmfreq = gd->arch.cpm_clk;
  574. bd->bi_brgfreq = gd->arch.brg_clk;
  575. bd->bi_sccfreq = gd->arch.scc_clk;
  576. bd->bi_vco = gd->arch.vco_out;
  577. #endif /* CONFIG_CPM2 */
  578. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  579. bd->bi_pcifreq = gd->pci_clk;
  580. #endif
  581. #if defined(CONFIG_EXTRA_CLOCK)
  582. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  583. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  584. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  585. #endif
  586. return 0;
  587. }
  588. #endif
  589. #ifdef CONFIG_POST
  590. static int init_post(void)
  591. {
  592. post_bootmode_init();
  593. post_run(NULL, POST_ROM | post_bootmode_get(0));
  594. return 0;
  595. }
  596. #endif
  597. static int reloc_fdt(void)
  598. {
  599. #ifndef CONFIG_OF_EMBED
  600. if (gd->flags & GD_FLG_SKIP_RELOC)
  601. return 0;
  602. if (gd->new_fdt) {
  603. memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
  604. gd->fdt_blob = gd->new_fdt;
  605. }
  606. #endif
  607. return 0;
  608. }
  609. static int reloc_bootstage(void)
  610. {
  611. #ifdef CONFIG_BOOTSTAGE
  612. if (gd->flags & GD_FLG_SKIP_RELOC)
  613. return 0;
  614. if (gd->new_bootstage) {
  615. int size = bootstage_get_size();
  616. debug("Copying bootstage from %p to %p, size %x\n",
  617. gd->bootstage, gd->new_bootstage, size);
  618. memcpy(gd->new_bootstage, gd->bootstage, size);
  619. gd->bootstage = gd->new_bootstage;
  620. bootstage_relocate();
  621. }
  622. #endif
  623. return 0;
  624. }
  625. static int reloc_bloblist(void)
  626. {
  627. #ifdef CONFIG_BLOBLIST
  628. if (gd->flags & GD_FLG_SKIP_RELOC)
  629. return 0;
  630. if (gd->new_bloblist) {
  631. int size = CONFIG_BLOBLIST_SIZE;
  632. debug("Copying bloblist from %p to %p, size %x\n",
  633. gd->bloblist, gd->new_bloblist, size);
  634. memcpy(gd->new_bloblist, gd->bloblist, size);
  635. gd->bloblist = gd->new_bloblist;
  636. }
  637. #endif
  638. return 0;
  639. }
  640. static int setup_reloc(void)
  641. {
  642. if (gd->flags & GD_FLG_SKIP_RELOC) {
  643. debug("Skipping relocation due to flag\n");
  644. return 0;
  645. }
  646. #ifdef CONFIG_SYS_TEXT_BASE
  647. #ifdef ARM
  648. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  649. #elif defined(CONFIG_M68K)
  650. /*
  651. * On all ColdFire arch cpu, monitor code starts always
  652. * just after the default vector table location, so at 0x400
  653. */
  654. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  655. #elif !defined(CONFIG_SANDBOX)
  656. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  657. #endif
  658. #endif
  659. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  660. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  661. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  662. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  663. gd->start_addr_sp);
  664. return 0;
  665. }
  666. #ifdef CONFIG_OF_BOARD_FIXUP
  667. static int fix_fdt(void)
  668. {
  669. return board_fix_fdt((void *)gd->fdt_blob);
  670. }
  671. #endif
  672. /* ARM calls relocate_code from its crt0.S */
  673. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  674. !CONFIG_IS_ENABLED(X86_64)
  675. static int jump_to_copy(void)
  676. {
  677. if (gd->flags & GD_FLG_SKIP_RELOC)
  678. return 0;
  679. /*
  680. * x86 is special, but in a nice way. It uses a trampoline which
  681. * enables the dcache if possible.
  682. *
  683. * For now, other archs use relocate_code(), which is implemented
  684. * similarly for all archs. When we do generic relocation, hopefully
  685. * we can make all archs enable the dcache prior to relocation.
  686. */
  687. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  688. /*
  689. * SDRAM and console are now initialised. The final stack can now
  690. * be setup in SDRAM. Code execution will continue in Flash, but
  691. * with the stack in SDRAM and Global Data in temporary memory
  692. * (CPU cache)
  693. */
  694. arch_setup_gd(gd->new_gd);
  695. board_init_f_r_trampoline(gd->start_addr_sp);
  696. #else
  697. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  698. #endif
  699. return 0;
  700. }
  701. #endif
  702. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  703. static int initf_bootstage(void)
  704. {
  705. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  706. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  707. int ret;
  708. ret = bootstage_init(!from_spl);
  709. if (ret)
  710. return ret;
  711. if (from_spl) {
  712. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  713. CONFIG_BOOTSTAGE_STASH_SIZE);
  714. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  715. if (ret && ret != -ENOENT) {
  716. debug("Failed to unstash bootstage: err=%d\n", ret);
  717. return ret;
  718. }
  719. }
  720. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  721. return 0;
  722. }
  723. static int initf_console_record(void)
  724. {
  725. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  726. return console_record_init();
  727. #else
  728. return 0;
  729. #endif
  730. }
  731. static int initf_dm(void)
  732. {
  733. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  734. int ret;
  735. bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
  736. ret = dm_init_and_scan(true);
  737. bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
  738. if (ret)
  739. return ret;
  740. #endif
  741. #ifdef CONFIG_TIMER_EARLY
  742. ret = dm_timer_init();
  743. if (ret)
  744. return ret;
  745. #endif
  746. return 0;
  747. }
  748. /* Architecture-specific memory reservation */
  749. __weak int reserve_arch(void)
  750. {
  751. return 0;
  752. }
  753. __weak int arch_cpu_init_dm(void)
  754. {
  755. return 0;
  756. }
  757. __weak int checkcpu(void)
  758. {
  759. return 0;
  760. }
  761. __weak int clear_bss(void)
  762. {
  763. return 0;
  764. }
  765. static const init_fnc_t init_sequence_f[] = {
  766. setup_mon_len,
  767. #ifdef CONFIG_OF_CONTROL
  768. fdtdec_setup,
  769. #endif
  770. #ifdef CONFIG_TRACE_EARLY
  771. trace_early_init,
  772. #endif
  773. initf_malloc,
  774. log_init,
  775. initf_bootstage, /* uses its own timer, so does not need DM */
  776. #ifdef CONFIG_BLOBLIST
  777. bloblist_init,
  778. #endif
  779. setup_spl_handoff,
  780. initf_console_record,
  781. #if defined(CONFIG_HAVE_FSP)
  782. arch_fsp_init,
  783. #endif
  784. arch_cpu_init, /* basic arch cpu dependent setup */
  785. mach_cpu_init, /* SoC/machine dependent CPU setup */
  786. initf_dm,
  787. arch_cpu_init_dm,
  788. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  789. board_early_init_f,
  790. #endif
  791. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  792. /* get CPU and bus clocks according to the environment variable */
  793. get_clocks, /* get CPU and bus clocks (etc.) */
  794. #endif
  795. #if !defined(CONFIG_M68K)
  796. timer_init, /* initialize timer */
  797. #endif
  798. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  799. board_postclk_init,
  800. #endif
  801. env_init, /* initialize environment */
  802. init_baud_rate, /* initialze baudrate settings */
  803. serial_init, /* serial communications setup */
  804. console_init_f, /* stage 1 init of console */
  805. display_options, /* say that we are here */
  806. display_text_info, /* show debugging info if required */
  807. checkcpu,
  808. #if defined(CONFIG_SYSRESET)
  809. print_resetinfo,
  810. #endif
  811. #if defined(CONFIG_DISPLAY_CPUINFO)
  812. print_cpuinfo, /* display cpu info (and speed) */
  813. #endif
  814. #if defined(CONFIG_DTB_RESELECT)
  815. embedded_dtb_select,
  816. #endif
  817. #if defined(CONFIG_DISPLAY_BOARDINFO)
  818. show_board_info,
  819. #endif
  820. INIT_FUNC_WATCHDOG_INIT
  821. #if defined(CONFIG_MISC_INIT_F)
  822. misc_init_f,
  823. #endif
  824. INIT_FUNC_WATCHDOG_RESET
  825. #if defined(CONFIG_SYS_I2C)
  826. init_func_i2c,
  827. #endif
  828. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  829. init_func_vid,
  830. #endif
  831. announce_dram_init,
  832. dram_init, /* configure available RAM banks */
  833. #ifdef CONFIG_POST
  834. post_init_f,
  835. #endif
  836. INIT_FUNC_WATCHDOG_RESET
  837. #if defined(CONFIG_SYS_DRAM_TEST)
  838. testdram,
  839. #endif /* CONFIG_SYS_DRAM_TEST */
  840. INIT_FUNC_WATCHDOG_RESET
  841. #ifdef CONFIG_POST
  842. init_post,
  843. #endif
  844. INIT_FUNC_WATCHDOG_RESET
  845. /*
  846. * Now that we have DRAM mapped and working, we can
  847. * relocate the code and continue running from DRAM.
  848. *
  849. * Reserve memory at end of RAM for (top down in that order):
  850. * - area that won't get touched by U-Boot and Linux (optional)
  851. * - kernel log buffer
  852. * - protected RAM
  853. * - LCD framebuffer
  854. * - monitor code
  855. * - board info struct
  856. */
  857. setup_dest_addr,
  858. #ifdef CONFIG_PRAM
  859. reserve_pram,
  860. #endif
  861. reserve_round_4k,
  862. #ifdef CONFIG_ARM
  863. reserve_mmu,
  864. #endif
  865. reserve_video,
  866. reserve_trace,
  867. reserve_uboot,
  868. reserve_malloc,
  869. reserve_board,
  870. setup_machine,
  871. reserve_global_data,
  872. reserve_fdt,
  873. reserve_bootstage,
  874. reserve_bloblist,
  875. reserve_arch,
  876. reserve_stacks,
  877. dram_init_banksize,
  878. show_dram_config,
  879. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  880. defined(CONFIG_SH)
  881. setup_board_part1,
  882. #endif
  883. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  884. INIT_FUNC_WATCHDOG_RESET
  885. setup_board_part2,
  886. #endif
  887. display_new_sp,
  888. #ifdef CONFIG_OF_BOARD_FIXUP
  889. fix_fdt,
  890. #endif
  891. INIT_FUNC_WATCHDOG_RESET
  892. reloc_fdt,
  893. reloc_bootstage,
  894. reloc_bloblist,
  895. setup_reloc,
  896. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  897. copy_uboot_to_ram,
  898. do_elf_reloc_fixups,
  899. #endif
  900. clear_bss,
  901. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  902. !CONFIG_IS_ENABLED(X86_64)
  903. jump_to_copy,
  904. #endif
  905. NULL,
  906. };
  907. void board_init_f(ulong boot_flags)
  908. {
  909. gd->flags = boot_flags;
  910. gd->have_console = 0;
  911. if (initcall_run_list(init_sequence_f))
  912. hang();
  913. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  914. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  915. !defined(CONFIG_ARC)
  916. /* NOTREACHED - jump_to_copy() does not return */
  917. hang();
  918. #endif
  919. }
  920. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  921. /*
  922. * For now this code is only used on x86.
  923. *
  924. * init_sequence_f_r is the list of init functions which are run when
  925. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  926. * The following limitations must be considered when implementing an
  927. * '_f_r' function:
  928. * - 'static' variables are read-only
  929. * - Global Data (gd->xxx) is read/write
  930. *
  931. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  932. * supported). It _should_, if possible, copy global data to RAM and
  933. * initialise the CPU caches (to speed up the relocation process)
  934. *
  935. * NOTE: At present only x86 uses this route, but it is intended that
  936. * all archs will move to this when generic relocation is implemented.
  937. */
  938. static const init_fnc_t init_sequence_f_r[] = {
  939. #if !CONFIG_IS_ENABLED(X86_64)
  940. init_cache_f_r,
  941. #endif
  942. NULL,
  943. };
  944. void board_init_f_r(void)
  945. {
  946. if (initcall_run_list(init_sequence_f_r))
  947. hang();
  948. /*
  949. * The pre-relocation drivers may be using memory that has now gone
  950. * away. Mark serial as unavailable - this will fall back to the debug
  951. * UART if available.
  952. *
  953. * Do the same with log drivers since the memory may not be available.
  954. */
  955. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  956. #ifdef CONFIG_TIMER
  957. gd->timer = NULL;
  958. #endif
  959. /*
  960. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  961. * Transfer execution from Flash to RAM by calculating the address
  962. * of the in-RAM copy of board_init_r() and calling it
  963. */
  964. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  965. /* NOTREACHED - board_init_r() does not return */
  966. hang();
  967. }
  968. #endif /* CONFIG_X86 */