tegra20.dtsi 4.4 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. tegra_car: clock@60006000 {
  6. compatible = "nvidia,tegra20-car";
  7. reg = <0x60006000 0x1000>;
  8. #clock-cells = <1>;
  9. };
  10. clocks {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. osc: clock {
  14. compatible = "fixed-clock";
  15. #clock-cells = <0>;
  16. };
  17. };
  18. intc: interrupt-controller@50041000 {
  19. compatible = "nvidia,tegra20-gic";
  20. interrupt-controller;
  21. #interrupt-cells = <1>;
  22. reg = < 0x50041000 0x1000 >,
  23. < 0x50040100 0x0100 >;
  24. };
  25. i2c@7000c000 {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. compatible = "nvidia,tegra20-i2c";
  29. reg = <0x7000C000 0x100>;
  30. interrupts = < 70 >;
  31. /* PERIPH_ID_I2C1, PLL_P_OUT3 */
  32. clocks = <&tegra_car 12>, <&tegra_car 124>;
  33. };
  34. i2c@7000c400 {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. compatible = "nvidia,tegra20-i2c";
  38. reg = <0x7000C400 0x100>;
  39. interrupts = < 116 >;
  40. /* PERIPH_ID_I2C2, PLL_P_OUT3 */
  41. clocks = <&tegra_car 54>, <&tegra_car 124>;
  42. };
  43. i2c@7000c500 {
  44. #address-cells = <1>;
  45. #size-cells = <0>;
  46. compatible = "nvidia,tegra20-i2c";
  47. reg = <0x7000C500 0x100>;
  48. interrupts = < 124 >;
  49. /* PERIPH_ID_I2C3, PLL_P_OUT3 */
  50. clocks = <&tegra_car 67>, <&tegra_car 124>;
  51. };
  52. i2c@7000d000 {
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. compatible = "nvidia,tegra20-i2c-dvc";
  56. reg = <0x7000D000 0x200>;
  57. interrupts = < 85 >;
  58. /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
  59. clocks = <&tegra_car 47>, <&tegra_car 124>;
  60. };
  61. i2s@70002800 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. compatible = "nvidia,tegra20-i2s";
  65. reg = <0x70002800 0x200>;
  66. interrupts = < 45 >;
  67. dma-channel = < 2 >;
  68. };
  69. i2s@70002a00 {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. compatible = "nvidia,tegra20-i2s";
  73. reg = <0x70002a00 0x200>;
  74. interrupts = < 35 >;
  75. dma-channel = < 1 >;
  76. };
  77. das@70000c00 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. compatible = "nvidia,tegra20-das";
  81. reg = <0x70000c00 0x80>;
  82. };
  83. gpio: gpio@6000d000 {
  84. compatible = "nvidia,tegra20-gpio";
  85. reg = < 0x6000d000 0x1000 >;
  86. interrupts = < 64 65 66 67 87 119 121 >;
  87. #gpio-cells = <2>;
  88. gpio-controller;
  89. };
  90. pinmux: pinmux@70000000 {
  91. compatible = "nvidia,tegra20-pinmux";
  92. reg = < 0x70000014 0x10 /* Tri-state registers */
  93. 0x70000080 0x20 /* Mux registers */
  94. 0x700000a0 0x14 /* Pull-up/down registers */
  95. 0x70000868 0xa8 >; /* Pad control registers */
  96. };
  97. serial@70006000 {
  98. compatible = "nvidia,tegra20-uart";
  99. reg = <0x70006000 0x40>;
  100. reg-shift = <2>;
  101. interrupts = < 68 >;
  102. };
  103. serial@70006040 {
  104. compatible = "nvidia,tegra20-uart";
  105. reg = <0x70006040 0x40>;
  106. reg-shift = <2>;
  107. interrupts = < 69 >;
  108. };
  109. serial@70006200 {
  110. compatible = "nvidia,tegra20-uart";
  111. reg = <0x70006200 0x100>;
  112. reg-shift = <2>;
  113. interrupts = < 78 >;
  114. };
  115. serial@70006300 {
  116. compatible = "nvidia,tegra20-uart";
  117. reg = <0x70006300 0x100>;
  118. reg-shift = <2>;
  119. interrupts = < 122 >;
  120. };
  121. serial@70006400 {
  122. compatible = "nvidia,tegra20-uart";
  123. reg = <0x70006400 0x100>;
  124. reg-shift = <2>;
  125. interrupts = < 123 >;
  126. };
  127. sdhci@c8000000 {
  128. compatible = "nvidia,tegra20-sdhci";
  129. reg = <0xc8000000 0x200>;
  130. interrupts = < 46 >;
  131. };
  132. sdhci@c8000200 {
  133. compatible = "nvidia,tegra20-sdhci";
  134. reg = <0xc8000200 0x200>;
  135. interrupts = < 47 >;
  136. };
  137. sdhci@c8000400 {
  138. compatible = "nvidia,tegra20-sdhci";
  139. reg = <0xc8000400 0x200>;
  140. interrupts = < 51 >;
  141. };
  142. sdhci@c8000600 {
  143. compatible = "nvidia,tegra20-sdhci";
  144. reg = <0xc8000600 0x200>;
  145. interrupts = < 63 >;
  146. };
  147. usb@c5000000 {
  148. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  149. reg = <0xc5000000 0x4000>;
  150. interrupts = < 52 >;
  151. phy_type = "utmi";
  152. clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
  153. nvidia,has-legacy-mode;
  154. };
  155. usb@c5004000 {
  156. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  157. reg = <0xc5004000 0x4000>;
  158. interrupts = < 53 >;
  159. phy_type = "ulpi";
  160. clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
  161. };
  162. usb@c5008000 {
  163. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  164. reg = <0xc5008000 0x4000>;
  165. interrupts = < 129 >;
  166. phy_type = "utmi";
  167. clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
  168. };
  169. emc@7000f400 {
  170. #address-cells = < 1 >;
  171. #size-cells = < 0 >;
  172. compatible = "nvidia,tegra20-emc";
  173. reg = <0x7000f400 0x200>;
  174. };
  175. kbc@7000e200 {
  176. compatible = "nvidia,tegra20-kbc";
  177. reg = <0x7000e200 0x0078>;
  178. };
  179. nand: nand-controller@70008000 {
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. compatible = "nvidia,tegra20-nand";
  183. reg = <0x70008000 0x100>;
  184. };
  185. };