scu.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2018 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <dm.h>
  11. #include <dm/lists.h>
  12. #include <dm/root.h>
  13. #include <dm/device-internal.h>
  14. #include <asm/arch/sci/sci.h>
  15. #include <linux/bitops.h>
  16. #include <linux/iopoll.h>
  17. #include <misc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct mu_type {
  20. u32 tr[4];
  21. u32 rr[4];
  22. u32 sr;
  23. u32 cr;
  24. };
  25. struct imx8_scu {
  26. struct mu_type *base;
  27. };
  28. #define MU_CR_GIE_MASK 0xF0000000u
  29. #define MU_CR_RIE_MASK 0xF000000u
  30. #define MU_CR_GIR_MASK 0xF0000u
  31. #define MU_CR_TIE_MASK 0xF00000u
  32. #define MU_CR_F_MASK 0x7u
  33. #define MU_SR_TE0_MASK BIT(23)
  34. #define MU_SR_RF0_MASK BIT(27)
  35. #define MU_TR_COUNT 4
  36. #define MU_RR_COUNT 4
  37. static inline void mu_hal_init(struct mu_type *base)
  38. {
  39. /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
  40. clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
  41. MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
  42. }
  43. static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
  44. {
  45. u32 mask = MU_SR_TE0_MASK >> reg_index;
  46. u32 val;
  47. int ret;
  48. assert(reg_index < MU_TR_COUNT);
  49. /* Wait TX register to be empty. */
  50. ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
  51. if (ret < 0) {
  52. printf("%s timeout\n", __func__);
  53. return -ETIMEDOUT;
  54. }
  55. writel(msg, &base->tr[reg_index]);
  56. return 0;
  57. }
  58. static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
  59. {
  60. u32 mask = MU_SR_RF0_MASK >> reg_index;
  61. u32 val;
  62. int ret;
  63. assert(reg_index < MU_TR_COUNT);
  64. /* Wait RX register to be full. */
  65. ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
  66. if (ret < 0) {
  67. printf("%s timeout\n", __func__);
  68. return -ETIMEDOUT;
  69. }
  70. *msg = readl(&base->rr[reg_index]);
  71. return 0;
  72. }
  73. static int sc_ipc_read(struct mu_type *base, void *data)
  74. {
  75. struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
  76. int ret;
  77. u8 count = 0;
  78. if (!msg)
  79. return -EINVAL;
  80. /* Read first word */
  81. ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
  82. if (ret)
  83. return ret;
  84. count++;
  85. /* Check size */
  86. if (msg->size > SC_RPC_MAX_MSG) {
  87. *((u32 *)msg) = 0;
  88. return -EINVAL;
  89. }
  90. /* Read remaining words */
  91. while (count < msg->size) {
  92. ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
  93. &msg->DATA.u32[count - 1]);
  94. if (ret)
  95. return ret;
  96. count++;
  97. }
  98. return 0;
  99. }
  100. static int sc_ipc_write(struct mu_type *base, void *data)
  101. {
  102. struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
  103. int ret;
  104. u8 count = 0;
  105. if (!msg)
  106. return -EINVAL;
  107. /* Check size */
  108. if (msg->size > SC_RPC_MAX_MSG)
  109. return -EINVAL;
  110. /* Write first word */
  111. ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
  112. if (ret)
  113. return ret;
  114. count++;
  115. /* Write remaining words */
  116. while (count < msg->size) {
  117. ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
  118. msg->DATA.u32[count - 1]);
  119. if (ret)
  120. return ret;
  121. count++;
  122. }
  123. return 0;
  124. }
  125. /*
  126. * Note the function prototype use msgid as the 2nd parameter, here
  127. * we take it as no_resp.
  128. */
  129. static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
  130. int tx_size, void *rx_msg, int rx_size)
  131. {
  132. struct imx8_scu *plat = dev_get_plat(dev);
  133. sc_err_t result;
  134. int ret;
  135. /* Expect tx_msg, rx_msg are the same value */
  136. if (rx_msg && tx_msg != rx_msg)
  137. printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
  138. ret = sc_ipc_write(plat->base, tx_msg);
  139. if (ret)
  140. return ret;
  141. if (!no_resp) {
  142. ret = sc_ipc_read(plat->base, rx_msg);
  143. if (ret)
  144. return ret;
  145. }
  146. result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);
  147. return sc_err_to_linux(result);
  148. }
  149. static int imx8_scu_probe(struct udevice *dev)
  150. {
  151. struct imx8_scu *plat = dev_get_plat(dev);
  152. fdt_addr_t addr;
  153. debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
  154. addr = dev_read_addr(dev);
  155. if (addr == FDT_ADDR_T_NONE)
  156. return -EINVAL;
  157. #ifdef CONFIG_SPL_BUILD
  158. plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
  159. #else
  160. plat->base = (struct mu_type *)addr;
  161. #endif
  162. /* U-Boot not enable interrupts, so need to enable RX interrupts */
  163. mu_hal_init(plat->base);
  164. gd->arch.scu_dev = dev;
  165. return 0;
  166. }
  167. static int imx8_scu_remove(struct udevice *dev)
  168. {
  169. return 0;
  170. }
  171. static int imx8_scu_bind(struct udevice *dev)
  172. {
  173. int ret;
  174. struct udevice *child;
  175. ofnode node;
  176. debug("%s(dev=%p)\n", __func__, dev);
  177. ofnode_for_each_subnode(node, dev_ofnode(dev)) {
  178. ret = lists_bind_fdt(dev, node, &child, true);
  179. if (ret)
  180. return ret;
  181. debug("bind child dev %s\n", child->name);
  182. }
  183. return 0;
  184. }
  185. static struct misc_ops imx8_scu_ops = {
  186. .call = imx8_scu_call,
  187. };
  188. static const struct udevice_id imx8_scu_ids[] = {
  189. { .compatible = "fsl,imx8qxp-mu" },
  190. { .compatible = "fsl,imx8-mu" },
  191. { }
  192. };
  193. U_BOOT_DRIVER(imx8_scu) = {
  194. .name = "imx8_scu",
  195. .id = UCLASS_MISC,
  196. .of_match = imx8_scu_ids,
  197. .probe = imx8_scu_probe,
  198. .bind = imx8_scu_bind,
  199. .remove = imx8_scu_remove,
  200. .ops = &imx8_scu_ops,
  201. .plat_auto = sizeof(struct imx8_scu),
  202. .flags = DM_FLAG_PRE_RELOC,
  203. };