nx_gpio.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Nexell
  4. * DeokJin, Lee <truevirtue@nexell.co.kr>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <asm/gpio.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. struct nx_gpio_regs {
  14. u32 data; /* Data register */
  15. u32 outputenb; /* Output Enable register */
  16. u32 detmode[2]; /* Detect Mode Register */
  17. u32 intenb; /* Interrupt Enable Register */
  18. u32 det; /* Event Detect Register */
  19. u32 pad; /* Pad Status Register */
  20. };
  21. struct nx_alive_gpio_regs {
  22. u32 pwrgate; /* Power Gating Register */
  23. u32 reserved0[28]; /* Reserved0 */
  24. u32 outputenb_reset;/* Alive GPIO Output Enable Reset Register */
  25. u32 outputenb; /* Alive GPIO Output Enable Register */
  26. u32 outputenb_read; /* Alive GPIO Output Read Register */
  27. u32 reserved1[3]; /* Reserved1 */
  28. u32 pad_reset; /* Alive GPIO Output Reset Register */
  29. u32 data; /* Alive GPIO Output Register */
  30. u32 pad_read; /* Alive GPIO Pad Read Register */
  31. u32 reserved2[33]; /* Reserved2 */
  32. u32 pad; /* Alive GPIO Input Value Register */
  33. };
  34. struct nx_gpio_platdata {
  35. void *regs;
  36. int gpio_count;
  37. const char *bank_name;
  38. };
  39. static int nx_alive_gpio_is_check(struct udevice *dev)
  40. {
  41. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  42. const char *bank_name = plat->bank_name;
  43. if (!strcmp(bank_name, "gpio_alv"))
  44. return 1;
  45. return 0;
  46. }
  47. static int nx_alive_gpio_direction_input(struct udevice *dev, unsigned int pin)
  48. {
  49. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  50. struct nx_alive_gpio_regs *const regs = plat->regs;
  51. setbits_le32(&regs->outputenb_reset, 1 << pin);
  52. return 0;
  53. }
  54. static int nx_alive_gpio_direction_output(struct udevice *dev, unsigned int pin,
  55. int val)
  56. {
  57. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  58. struct nx_alive_gpio_regs *const regs = plat->regs;
  59. if (val)
  60. setbits_le32(&regs->data, 1 << pin);
  61. else
  62. setbits_le32(&regs->pad_reset, 1 << pin);
  63. setbits_le32(&regs->outputenb, 1 << pin);
  64. return 0;
  65. }
  66. static int nx_alive_gpio_get_value(struct udevice *dev, unsigned int pin)
  67. {
  68. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  69. struct nx_alive_gpio_regs *const regs = plat->regs;
  70. unsigned int mask = 1UL << pin;
  71. unsigned int value;
  72. value = (readl(&regs->pad_read) & mask) >> pin;
  73. return value;
  74. }
  75. static int nx_alive_gpio_set_value(struct udevice *dev, unsigned int pin,
  76. int val)
  77. {
  78. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  79. struct nx_alive_gpio_regs *const regs = plat->regs;
  80. if (val)
  81. setbits_le32(&regs->data, 1 << pin);
  82. else
  83. clrbits_le32(&regs->pad_reset, 1 << pin);
  84. return 0;
  85. }
  86. static int nx_alive_gpio_get_function(struct udevice *dev, unsigned int pin)
  87. {
  88. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  89. struct nx_alive_gpio_regs *const regs = plat->regs;
  90. unsigned int mask = (1UL << pin);
  91. unsigned int output;
  92. output = readl(&regs->outputenb_read) & mask;
  93. if (output)
  94. return GPIOF_OUTPUT;
  95. else
  96. return GPIOF_INPUT;
  97. }
  98. static int nx_gpio_direction_input(struct udevice *dev, unsigned int pin)
  99. {
  100. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  101. struct nx_gpio_regs *const regs = plat->regs;
  102. if (nx_alive_gpio_is_check(dev))
  103. return nx_alive_gpio_direction_input(dev, pin);
  104. clrbits_le32(&regs->outputenb, 1 << pin);
  105. return 0;
  106. }
  107. static int nx_gpio_direction_output(struct udevice *dev, unsigned int pin,
  108. int val)
  109. {
  110. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  111. struct nx_gpio_regs *const regs = plat->regs;
  112. if (nx_alive_gpio_is_check(dev))
  113. return nx_alive_gpio_direction_output(dev, pin, val);
  114. if (val)
  115. setbits_le32(&regs->data, 1 << pin);
  116. else
  117. clrbits_le32(&regs->data, 1 << pin);
  118. setbits_le32(&regs->outputenb, 1 << pin);
  119. return 0;
  120. }
  121. static int nx_gpio_get_value(struct udevice *dev, unsigned int pin)
  122. {
  123. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  124. struct nx_gpio_regs *const regs = plat->regs;
  125. unsigned int mask = 1UL << pin;
  126. unsigned int value;
  127. if (nx_alive_gpio_is_check(dev))
  128. return nx_alive_gpio_get_value(dev, pin);
  129. value = (readl(&regs->pad) & mask) >> pin;
  130. return value;
  131. }
  132. static int nx_gpio_set_value(struct udevice *dev, unsigned int pin, int val)
  133. {
  134. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  135. struct nx_gpio_regs *const regs = plat->regs;
  136. if (nx_alive_gpio_is_check(dev))
  137. return nx_alive_gpio_set_value(dev, pin, val);
  138. if (val)
  139. setbits_le32(&regs->data, 1 << pin);
  140. else
  141. clrbits_le32(&regs->data, 1 << pin);
  142. return 0;
  143. }
  144. static int nx_gpio_get_function(struct udevice *dev, unsigned int pin)
  145. {
  146. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  147. struct nx_gpio_regs *const regs = plat->regs;
  148. unsigned int mask = (1UL << pin);
  149. unsigned int output;
  150. if (nx_alive_gpio_is_check(dev))
  151. return nx_alive_gpio_get_function(dev, pin);
  152. output = readl(&regs->outputenb) & mask;
  153. if (output)
  154. return GPIOF_OUTPUT;
  155. else
  156. return GPIOF_INPUT;
  157. }
  158. static int nx_gpio_probe(struct udevice *dev)
  159. {
  160. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  161. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  162. uc_priv->gpio_count = plat->gpio_count;
  163. uc_priv->bank_name = plat->bank_name;
  164. return 0;
  165. }
  166. static int nx_gpio_ofdata_to_platdata(struct udevice *dev)
  167. {
  168. struct nx_gpio_platdata *plat = dev_get_plat(dev);
  169. plat->regs = map_physmem(devfdt_get_addr(dev),
  170. sizeof(struct nx_gpio_regs),
  171. MAP_NOCACHE);
  172. plat->gpio_count = dev_read_s32_default(dev, "nexell,gpio-bank-width",
  173. 32);
  174. plat->bank_name = dev_read_string(dev, "gpio-bank-name");
  175. return 0;
  176. }
  177. static const struct dm_gpio_ops nx_gpio_ops = {
  178. .direction_input = nx_gpio_direction_input,
  179. .direction_output = nx_gpio_direction_output,
  180. .get_value = nx_gpio_get_value,
  181. .set_value = nx_gpio_set_value,
  182. .get_function = nx_gpio_get_function,
  183. };
  184. static const struct udevice_id nx_gpio_ids[] = {
  185. { .compatible = "nexell,nexell-gpio" },
  186. { }
  187. };
  188. U_BOOT_DRIVER(nx_gpio) = {
  189. .name = "nx_gpio",
  190. .id = UCLASS_GPIO,
  191. .of_match = nx_gpio_ids,
  192. .ops = &nx_gpio_ops,
  193. .ofdata_to_platdata = nx_gpio_ofdata_to_platdata,
  194. .plat_auto = sizeof(struct nx_gpio_platdata),
  195. .probe = nx_gpio_probe,
  196. };