intel_broadwell_gpio.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <log.h>
  10. #include <pch.h>
  11. #include <pci.h>
  12. #include <syscon.h>
  13. #include <asm/cpu.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/pci.h>
  17. #include <asm/arch/gpio.h>
  18. #include <dt-bindings/gpio/x86-gpio.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /**
  21. * struct broadwell_bank_priv - Private driver data
  22. *
  23. * @regs: Pointer to GPIO registers
  24. * @bank: Bank number for this bank (0, 1 or 2)
  25. * @offset: GPIO offset for this bank (0, 32 or 64)
  26. */
  27. struct broadwell_bank_priv {
  28. struct pch_lp_gpio_regs *regs;
  29. int bank;
  30. int offset;
  31. };
  32. static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
  33. const char *label)
  34. {
  35. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  36. struct pch_lp_gpio_regs *regs = priv->regs;
  37. u32 val;
  38. /*
  39. * Make sure that the GPIO pin we want isn't already in use for some
  40. * built-in hardware function. We have to check this for every
  41. * requested pin.
  42. */
  43. debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
  44. val = inl(&regs->own[priv->bank]);
  45. if (!(val & (1UL << offset))) {
  46. debug("gpio is reserved for internal use\n");
  47. return -EPERM;
  48. }
  49. debug("ok\n");
  50. return 0;
  51. }
  52. static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
  53. {
  54. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  55. struct pch_lp_gpio_regs *regs = priv->regs;
  56. setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
  57. return 0;
  58. }
  59. static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
  60. {
  61. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  62. struct pch_lp_gpio_regs *regs = priv->regs;
  63. return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
  64. 1 : 0;
  65. }
  66. static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
  67. int value)
  68. {
  69. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  70. struct pch_lp_gpio_regs *regs = priv->regs;
  71. debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
  72. value);
  73. clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH,
  74. value ? CONFA_OUTPUT_HIGH : 0);
  75. return 0;
  76. }
  77. static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset,
  78. int value)
  79. {
  80. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  81. struct pch_lp_gpio_regs *regs = priv->regs;
  82. broadwell_gpio_set_value(dev, offset, value);
  83. clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
  84. return 0;
  85. }
  86. static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
  87. {
  88. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  89. struct pch_lp_gpio_regs *regs = priv->regs;
  90. u32 mask = 1UL << offset;
  91. if (!(inl(&regs->own[priv->bank]) & mask))
  92. return GPIOF_FUNC;
  93. if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT)
  94. return GPIOF_INPUT;
  95. else
  96. return GPIOF_OUTPUT;
  97. }
  98. static int broadwell_gpio_probe(struct udevice *dev)
  99. {
  100. struct broadwell_bank_platdata *plat = dev_get_plat(dev);
  101. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  102. struct broadwell_bank_priv *priv = dev_get_priv(dev);
  103. struct udevice *pinctrl;
  104. int ret;
  105. /* Set up pin control if available */
  106. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
  107. debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
  108. uc_priv->gpio_count = GPIO_PER_BANK;
  109. uc_priv->bank_name = plat->bank_name;
  110. priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
  111. priv->bank = plat->bank;
  112. priv->offset = priv->bank * 32;
  113. debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
  114. priv->bank);
  115. return 0;
  116. }
  117. static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev)
  118. {
  119. struct broadwell_bank_platdata *plat = dev_get_plat(dev);
  120. u32 gpiobase;
  121. int bank;
  122. int ret;
  123. ret = pch_get_gpio_base(dev->parent, &gpiobase);
  124. if (ret)
  125. return ret;
  126. bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
  127. if (bank == -1) {
  128. debug("%s: Invalid bank number %d\n", __func__, bank);
  129. return -EINVAL;
  130. }
  131. plat->bank = bank;
  132. plat->base_addr = gpiobase;
  133. plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  134. "bank-name", NULL);
  135. return 0;
  136. }
  137. static const struct dm_gpio_ops gpio_broadwell_ops = {
  138. .request = broadwell_gpio_request,
  139. .direction_input = broadwell_gpio_direction_input,
  140. .direction_output = broadwell_gpio_direction_output,
  141. .get_value = broadwell_gpio_get_value,
  142. .set_value = broadwell_gpio_set_value,
  143. .get_function = broadwell_gpio_get_function,
  144. };
  145. static const struct udevice_id intel_broadwell_gpio_ids[] = {
  146. { .compatible = "intel,broadwell-gpio" },
  147. { }
  148. };
  149. U_BOOT_DRIVER(gpio_broadwell) = {
  150. .name = "gpio_broadwell",
  151. .id = UCLASS_GPIO,
  152. .of_match = intel_broadwell_gpio_ids,
  153. .ops = &gpio_broadwell_ops,
  154. .ofdata_to_platdata = broadwell_gpio_ofdata_to_platdata,
  155. .probe = broadwell_gpio_probe,
  156. .priv_auto = sizeof(struct broadwell_bank_priv),
  157. .plat_auto = sizeof(struct broadwell_bank_platdata),
  158. };