at91_gpio.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
  4. *
  5. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  6. *
  7. * Copyright (C) 2005 HP Labs
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <linux/sizes.h>
  16. #include <asm/gpio.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/at91_pio.h>
  19. #define GPIO_PER_BANK 32
  20. static struct at91_port *at91_pio_get_port(unsigned port)
  21. {
  22. switch (port) {
  23. case AT91_PIO_PORTA:
  24. return (struct at91_port *)ATMEL_BASE_PIOA;
  25. case AT91_PIO_PORTB:
  26. return (struct at91_port *)ATMEL_BASE_PIOB;
  27. case AT91_PIO_PORTC:
  28. return (struct at91_port *)ATMEL_BASE_PIOC;
  29. #if (ATMEL_PIO_PORTS > 3)
  30. case AT91_PIO_PORTD:
  31. return (struct at91_port *)ATMEL_BASE_PIOD;
  32. #if (ATMEL_PIO_PORTS > 4)
  33. case AT91_PIO_PORTE:
  34. return (struct at91_port *)ATMEL_BASE_PIOE;
  35. #endif
  36. #endif
  37. default:
  38. printf("Error: at91_gpio: Fail to get PIO base!\n");
  39. return NULL;
  40. }
  41. }
  42. static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
  43. int use_pullup)
  44. {
  45. u32 mask;
  46. mask = 1 << offset;
  47. if (use_pullup)
  48. writel(mask, &at91_port->puer);
  49. else
  50. writel(mask, &at91_port->pudr);
  51. writel(mask, &at91_port->per);
  52. }
  53. int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  54. {
  55. struct at91_port *at91_port = at91_pio_get_port(port);
  56. if (at91_port && (pin < GPIO_PER_BANK))
  57. at91_set_port_pullup(at91_port, pin, use_pullup);
  58. return 0;
  59. }
  60. /*
  61. * mux the pin to the "GPIO" peripheral role.
  62. */
  63. int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
  64. {
  65. struct at91_port *at91_port = at91_pio_get_port(port);
  66. u32 mask;
  67. if (at91_port && (pin < GPIO_PER_BANK)) {
  68. mask = 1 << pin;
  69. writel(mask, &at91_port->idr);
  70. at91_set_pio_pullup(port, pin, use_pullup);
  71. writel(mask, &at91_port->per);
  72. }
  73. return 0;
  74. }
  75. /*
  76. * mux the pin to the "A" internal peripheral role.
  77. */
  78. int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  79. {
  80. struct at91_port *at91_port = at91_pio_get_port(port);
  81. u32 mask;
  82. if (at91_port && (pin < GPIO_PER_BANK)) {
  83. mask = 1 << pin;
  84. writel(mask, &at91_port->idr);
  85. at91_set_pio_pullup(port, pin, use_pullup);
  86. writel(mask, &at91_port->mux.pio2.asr);
  87. writel(mask, &at91_port->pdr);
  88. }
  89. return 0;
  90. }
  91. /*
  92. * mux the pin to the "B" internal peripheral role.
  93. */
  94. int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  95. {
  96. struct at91_port *at91_port = at91_pio_get_port(port);
  97. u32 mask;
  98. if (at91_port && (pin < GPIO_PER_BANK)) {
  99. mask = 1 << pin;
  100. writel(mask, &at91_port->idr);
  101. at91_set_pio_pullup(port, pin, use_pullup);
  102. writel(mask, &at91_port->mux.pio2.bsr);
  103. writel(mask, &at91_port->pdr);
  104. }
  105. return 0;
  106. }
  107. /*
  108. * mux the pin to the "A" internal peripheral role.
  109. */
  110. int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  111. {
  112. struct at91_port *at91_port = at91_pio_get_port(port);
  113. u32 mask;
  114. if (at91_port && (pin < GPIO_PER_BANK)) {
  115. mask = 1 << pin;
  116. writel(mask, &at91_port->idr);
  117. at91_set_pio_pullup(port, pin, use_pullup);
  118. writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
  119. &at91_port->mux.pio3.abcdsr1);
  120. writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
  121. &at91_port->mux.pio3.abcdsr2);
  122. writel(mask, &at91_port->pdr);
  123. }
  124. return 0;
  125. }
  126. /*
  127. * mux the pin to the "B" internal peripheral role.
  128. */
  129. int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  130. {
  131. struct at91_port *at91_port = at91_pio_get_port(port);
  132. u32 mask;
  133. if (at91_port && (pin < GPIO_PER_BANK)) {
  134. mask = 1 << pin;
  135. writel(mask, &at91_port->idr);
  136. at91_set_pio_pullup(port, pin, use_pullup);
  137. writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
  138. &at91_port->mux.pio3.abcdsr1);
  139. writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
  140. &at91_port->mux.pio3.abcdsr2);
  141. writel(mask, &at91_port->pdr);
  142. }
  143. return 0;
  144. }
  145. /*
  146. * mux the pin to the "C" internal peripheral role.
  147. */
  148. int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
  149. {
  150. struct at91_port *at91_port = at91_pio_get_port(port);
  151. u32 mask;
  152. if (at91_port && (pin < GPIO_PER_BANK)) {
  153. mask = 1 << pin;
  154. writel(mask, &at91_port->idr);
  155. at91_set_pio_pullup(port, pin, use_pullup);
  156. writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
  157. &at91_port->mux.pio3.abcdsr1);
  158. writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
  159. &at91_port->mux.pio3.abcdsr2);
  160. writel(mask, &at91_port->pdr);
  161. }
  162. return 0;
  163. }
  164. /*
  165. * mux the pin to the "D" internal peripheral role.
  166. */
  167. int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
  168. {
  169. struct at91_port *at91_port = at91_pio_get_port(port);
  170. u32 mask;
  171. if (at91_port && (pin < GPIO_PER_BANK)) {
  172. mask = 1 << pin;
  173. writel(mask, &at91_port->idr);
  174. at91_set_pio_pullup(port, pin, use_pullup);
  175. writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
  176. &at91_port->mux.pio3.abcdsr1);
  177. writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
  178. &at91_port->mux.pio3.abcdsr2);
  179. writel(mask, &at91_port->pdr);
  180. }
  181. return 0;
  182. }
  183. #if CONFIG_IS_ENABLED(DM_GPIO)
  184. static bool at91_get_port_output(struct at91_port *at91_port, int offset)
  185. {
  186. u32 mask, val;
  187. mask = 1 << offset;
  188. val = readl(&at91_port->osr);
  189. return val & mask;
  190. }
  191. #endif
  192. static void at91_set_port_input(struct at91_port *at91_port, int offset,
  193. int use_pullup)
  194. {
  195. u32 mask;
  196. mask = 1 << offset;
  197. writel(mask, &at91_port->idr);
  198. at91_set_port_pullup(at91_port, offset, use_pullup);
  199. writel(mask, &at91_port->odr);
  200. writel(mask, &at91_port->per);
  201. }
  202. /*
  203. * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
  204. * configure it for an input.
  205. */
  206. int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
  207. {
  208. struct at91_port *at91_port = at91_pio_get_port(port);
  209. if (at91_port && (pin < GPIO_PER_BANK))
  210. at91_set_port_input(at91_port, pin, use_pullup);
  211. return 0;
  212. }
  213. static void at91_set_port_output(struct at91_port *at91_port, int offset,
  214. int value)
  215. {
  216. u32 mask;
  217. mask = 1 << offset;
  218. writel(mask, &at91_port->idr);
  219. writel(mask, &at91_port->pudr);
  220. if (value)
  221. writel(mask, &at91_port->sodr);
  222. else
  223. writel(mask, &at91_port->codr);
  224. writel(mask, &at91_port->oer);
  225. writel(mask, &at91_port->per);
  226. }
  227. /*
  228. * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
  229. * and configure it for an output.
  230. */
  231. int at91_set_pio_output(unsigned port, u32 pin, int value)
  232. {
  233. struct at91_port *at91_port = at91_pio_get_port(port);
  234. if (at91_port && (pin < GPIO_PER_BANK))
  235. at91_set_port_output(at91_port, pin, value);
  236. return 0;
  237. }
  238. /*
  239. * enable/disable the glitch filter. mostly used with IRQ handling.
  240. */
  241. int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  242. {
  243. struct at91_port *at91_port = at91_pio_get_port(port);
  244. u32 mask;
  245. if (at91_port && (pin < GPIO_PER_BANK)) {
  246. mask = 1 << pin;
  247. if (is_on)
  248. writel(mask, &at91_port->ifer);
  249. else
  250. writel(mask, &at91_port->ifdr);
  251. }
  252. return 0;
  253. }
  254. /*
  255. * enable/disable the glitch filter. mostly used with IRQ handling.
  256. */
  257. int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  258. {
  259. struct at91_port *at91_port = at91_pio_get_port(port);
  260. u32 mask;
  261. if (at91_port && (pin < GPIO_PER_BANK)) {
  262. mask = 1 << pin;
  263. if (is_on) {
  264. writel(mask, &at91_port->mux.pio3.ifscdr);
  265. writel(mask, &at91_port->ifer);
  266. } else {
  267. writel(mask, &at91_port->ifdr);
  268. }
  269. }
  270. return 0;
  271. }
  272. /*
  273. * enable/disable the debounce filter.
  274. */
  275. int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
  276. {
  277. struct at91_port *at91_port = at91_pio_get_port(port);
  278. u32 mask;
  279. if (at91_port && (pin < GPIO_PER_BANK)) {
  280. mask = 1 << pin;
  281. if (is_on) {
  282. writel(mask, &at91_port->mux.pio3.ifscer);
  283. writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
  284. writel(mask, &at91_port->ifer);
  285. } else {
  286. writel(mask, &at91_port->ifdr);
  287. }
  288. }
  289. return 0;
  290. }
  291. /*
  292. * enable/disable the pull-down.
  293. * If pull-up already enabled while calling the function, we disable it.
  294. */
  295. int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
  296. {
  297. struct at91_port *at91_port = at91_pio_get_port(port);
  298. u32 mask;
  299. if (at91_port && (pin < GPIO_PER_BANK)) {
  300. mask = 1 << pin;
  301. if (is_on) {
  302. at91_set_pio_pullup(port, pin, 0);
  303. writel(mask, &at91_port->mux.pio3.ppder);
  304. } else
  305. writel(mask, &at91_port->mux.pio3.ppddr);
  306. }
  307. return 0;
  308. }
  309. int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  310. {
  311. struct at91_port *at91_port = at91_pio_get_port(port);
  312. if (use_pullup)
  313. at91_pio3_set_pio_pulldown(port, pin, 0);
  314. if (at91_port && (pin < GPIO_PER_BANK))
  315. at91_set_port_pullup(at91_port, pin, use_pullup);
  316. return 0;
  317. }
  318. /*
  319. * disable Schmitt trigger
  320. */
  321. int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
  322. {
  323. struct at91_port *at91_port = at91_pio_get_port(port);
  324. u32 mask;
  325. if (at91_port && (pin < GPIO_PER_BANK)) {
  326. mask = 1 << pin;
  327. writel(readl(&at91_port->schmitt) | mask,
  328. &at91_port->schmitt);
  329. }
  330. return 0;
  331. }
  332. /*
  333. * enable/disable the multi-driver. This is only valid for output and
  334. * allows the output pin to run as an open collector output.
  335. */
  336. int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
  337. {
  338. struct at91_port *at91_port = at91_pio_get_port(port);
  339. u32 mask;
  340. if (at91_port && (pin < GPIO_PER_BANK)) {
  341. mask = 1 << pin;
  342. if (is_on)
  343. writel(mask, &at91_port->mder);
  344. else
  345. writel(mask, &at91_port->mddr);
  346. }
  347. return 0;
  348. }
  349. static void at91_set_port_value(struct at91_port *at91_port, int offset,
  350. int value)
  351. {
  352. u32 mask;
  353. mask = 1 << offset;
  354. if (value)
  355. writel(mask, &at91_port->sodr);
  356. else
  357. writel(mask, &at91_port->codr);
  358. }
  359. /*
  360. * assuming the pin is muxed as a gpio output, set its value.
  361. */
  362. int at91_set_pio_value(unsigned port, unsigned pin, int value)
  363. {
  364. struct at91_port *at91_port = at91_pio_get_port(port);
  365. if (at91_port && (pin < GPIO_PER_BANK))
  366. at91_set_port_value(at91_port, pin, value);
  367. return 0;
  368. }
  369. static int at91_get_port_value(struct at91_port *at91_port, int offset)
  370. {
  371. u32 pdsr = 0, mask;
  372. mask = 1 << offset;
  373. pdsr = readl(&at91_port->pdsr) & mask;
  374. return pdsr != 0;
  375. }
  376. /*
  377. * read the pin's value (works even if it's not muxed as a gpio).
  378. */
  379. int at91_get_pio_value(unsigned port, unsigned pin)
  380. {
  381. struct at91_port *at91_port = at91_pio_get_port(port);
  382. if (at91_port && (pin < GPIO_PER_BANK))
  383. return at91_get_port_value(at91_port, pin);
  384. return 0;
  385. }
  386. #if !CONFIG_IS_ENABLED(DM_GPIO)
  387. /* Common GPIO API */
  388. int gpio_request(unsigned gpio, const char *label)
  389. {
  390. return 0;
  391. }
  392. int gpio_free(unsigned gpio)
  393. {
  394. return 0;
  395. }
  396. int gpio_direction_input(unsigned gpio)
  397. {
  398. at91_set_pio_input(at91_gpio_to_port(gpio),
  399. at91_gpio_to_pin(gpio), 0);
  400. return 0;
  401. }
  402. int gpio_direction_output(unsigned gpio, int value)
  403. {
  404. at91_set_pio_output(at91_gpio_to_port(gpio),
  405. at91_gpio_to_pin(gpio), value);
  406. return 0;
  407. }
  408. int gpio_get_value(unsigned gpio)
  409. {
  410. return at91_get_pio_value(at91_gpio_to_port(gpio),
  411. at91_gpio_to_pin(gpio));
  412. }
  413. int gpio_set_value(unsigned gpio, int value)
  414. {
  415. at91_set_pio_value(at91_gpio_to_port(gpio),
  416. at91_gpio_to_pin(gpio), value);
  417. return 0;
  418. }
  419. #endif
  420. #if CONFIG_IS_ENABLED(DM_GPIO)
  421. struct at91_port_priv {
  422. struct at91_port *regs;
  423. };
  424. /* set GPIO pin 'gpio' as an input */
  425. static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
  426. {
  427. struct at91_port_priv *port = dev_get_priv(dev);
  428. at91_set_port_input(port->regs, offset, 0);
  429. return 0;
  430. }
  431. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  432. static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
  433. int value)
  434. {
  435. struct at91_port_priv *port = dev_get_priv(dev);
  436. at91_set_port_output(port->regs, offset, value);
  437. return 0;
  438. }
  439. /* read GPIO IN value of pin 'gpio' */
  440. static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
  441. {
  442. struct at91_port_priv *port = dev_get_priv(dev);
  443. return at91_get_port_value(port->regs, offset);
  444. }
  445. /* write GPIO OUT value to pin 'gpio' */
  446. static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
  447. int value)
  448. {
  449. struct at91_port_priv *port = dev_get_priv(dev);
  450. at91_set_port_value(port->regs, offset, value);
  451. return 0;
  452. }
  453. static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
  454. {
  455. struct at91_port_priv *port = dev_get_priv(dev);
  456. /* GPIOF_FUNC is not implemented yet */
  457. if (at91_get_port_output(port->regs, offset))
  458. return GPIOF_OUTPUT;
  459. else
  460. return GPIOF_INPUT;
  461. }
  462. static const char *at91_get_bank_name(uint32_t base_addr)
  463. {
  464. switch (base_addr) {
  465. case ATMEL_BASE_PIOA:
  466. return "PIOA";
  467. case ATMEL_BASE_PIOB:
  468. return "PIOB";
  469. case ATMEL_BASE_PIOC:
  470. return "PIOC";
  471. #if (ATMEL_PIO_PORTS > 3)
  472. case ATMEL_BASE_PIOD:
  473. return "PIOD";
  474. #if (ATMEL_PIO_PORTS > 4)
  475. case ATMEL_BASE_PIOE:
  476. return "PIOE";
  477. #endif
  478. #endif
  479. }
  480. return "undefined";
  481. }
  482. static const struct dm_gpio_ops gpio_at91_ops = {
  483. .direction_input = at91_gpio_direction_input,
  484. .direction_output = at91_gpio_direction_output,
  485. .get_value = at91_gpio_get_value,
  486. .set_value = at91_gpio_set_value,
  487. .get_function = at91_gpio_get_function,
  488. };
  489. static int at91_gpio_probe(struct udevice *dev)
  490. {
  491. struct at91_port_priv *port = dev_get_priv(dev);
  492. struct at91_port_platdata *plat = dev_get_plat(dev);
  493. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  494. struct clk clk;
  495. int ret;
  496. ret = clk_get_by_index(dev, 0, &clk);
  497. if (ret)
  498. return ret;
  499. ret = clk_enable(&clk);
  500. if (ret)
  501. return ret;
  502. clk_free(&clk);
  503. #if CONFIG_IS_ENABLED(OF_CONTROL)
  504. plat->base_addr = dev_read_addr(dev);
  505. #endif
  506. plat->bank_name = at91_get_bank_name(plat->base_addr);
  507. port->regs = (struct at91_port *)plat->base_addr;
  508. uc_priv->bank_name = plat->bank_name;
  509. uc_priv->gpio_count = GPIO_PER_BANK;
  510. return 0;
  511. }
  512. #if CONFIG_IS_ENABLED(OF_CONTROL)
  513. static const struct udevice_id at91_gpio_ids[] = {
  514. { .compatible = "atmel,at91rm9200-gpio" },
  515. { }
  516. };
  517. #endif
  518. U_BOOT_DRIVER(atmel_at91rm9200_gpio) = {
  519. .name = "atmel_at91rm9200_gpio",
  520. .id = UCLASS_GPIO,
  521. #if CONFIG_IS_ENABLED(OF_CONTROL)
  522. .of_match = at91_gpio_ids,
  523. .plat_auto = sizeof(struct at91_port_platdata),
  524. #endif
  525. .ops = &gpio_at91_ops,
  526. .probe = at91_gpio_probe,
  527. .priv_auto = sizeof(struct at91_port_priv),
  528. };
  529. #endif