clk_rk3368.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  6. */
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <syscon.h>
  16. #include <bitfield.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/cru_rk3368.h>
  19. #include <asm/arch-rockchip/hardware.h>
  20. #include <asm/io.h>
  21. #include <dm/lists.h>
  22. #include <dt-bindings/clock/rk3368-cru.h>
  23. #include <linux/delay.h>
  24. #include <linux/stringify.h>
  25. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  26. struct rk3368_clk_plat {
  27. struct dtd_rockchip_rk3368_cru dtd;
  28. };
  29. #endif
  30. struct pll_div {
  31. u32 nr;
  32. u32 nf;
  33. u32 no;
  34. };
  35. #define OSC_HZ (24 * 1000 * 1000)
  36. #define APLL_L_HZ (800 * 1000 * 1000)
  37. #define APLL_B_HZ (816 * 1000 * 1000)
  38. #define GPLL_HZ (576 * 1000 * 1000)
  39. #define CPLL_HZ (400 * 1000 * 1000)
  40. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  41. #define PLL_DIVISORS(hz, _nr, _no) { \
  42. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
  43. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  44. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
  45. "divisors on line " __stringify(__LINE__));
  46. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  47. static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
  48. static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
  49. #if !defined(CONFIG_TPL_BUILD)
  50. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
  51. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
  52. #endif
  53. #endif
  54. static ulong rk3368_clk_get_rate(struct clk *clk);
  55. /* Get pll rate by id */
  56. static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
  57. enum rk3368_pll_id pll_id)
  58. {
  59. uint32_t nr, no, nf;
  60. uint32_t con;
  61. struct rk3368_pll *pll = &cru->pll[pll_id];
  62. con = readl(&pll->con3);
  63. switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
  64. case PLL_MODE_SLOW:
  65. return OSC_HZ;
  66. case PLL_MODE_NORMAL:
  67. con = readl(&pll->con0);
  68. no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
  69. nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
  70. con = readl(&pll->con1);
  71. nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
  72. return (24 * nf / (nr * no)) * 1000000;
  73. case PLL_MODE_DEEP_SLOW:
  74. default:
  75. return 32768;
  76. }
  77. }
  78. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  79. static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
  80. const struct pll_div *div)
  81. {
  82. struct rk3368_pll *pll = &cru->pll[pll_id];
  83. /* All PLLs have same VCO and output frequency range restrictions*/
  84. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  85. uint output_hz = vco_hz / div->no;
  86. debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  87. pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  88. /* enter slow mode and reset pll */
  89. rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
  90. PLL_RESET << PLL_RESET_SHIFT);
  91. rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
  92. ((div->nr - 1) << PLL_NR_SHIFT) |
  93. ((div->no - 1) << PLL_OD_SHIFT));
  94. writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
  95. /*
  96. * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
  97. * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
  98. */
  99. clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  100. udelay(10);
  101. /* return from reset */
  102. rk_clrreg(&pll->con3, PLL_RESET_MASK);
  103. /* waiting for pll lock */
  104. while (!(readl(&pll->con1) & PLL_LOCK_STA))
  105. udelay(1);
  106. rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
  107. PLL_MODE_NORMAL << PLL_MODE_SHIFT);
  108. return 0;
  109. }
  110. #endif
  111. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  112. static void rkclk_init(struct rk3368_cru *cru)
  113. {
  114. u32 apllb, aplll, dpll, cpll, gpll;
  115. rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
  116. rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
  117. #if !defined(CONFIG_TPL_BUILD)
  118. /*
  119. * If we plan to return to the boot ROM, we can't increase the
  120. * GPLL rate from the SPL stage.
  121. */
  122. rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
  123. rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
  124. #endif
  125. apllb = rkclk_pll_get_rate(cru, APLLB);
  126. aplll = rkclk_pll_get_rate(cru, APLLL);
  127. dpll = rkclk_pll_get_rate(cru, DPLL);
  128. cpll = rkclk_pll_get_rate(cru, CPLL);
  129. gpll = rkclk_pll_get_rate(cru, GPLL);
  130. debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
  131. __func__, apllb, aplll, dpll, cpll, gpll);
  132. }
  133. #endif
  134. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  135. static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
  136. {
  137. u32 div, con, con_id, rate;
  138. u32 pll_rate;
  139. switch (clk_id) {
  140. case HCLK_SDMMC:
  141. con_id = 50;
  142. break;
  143. case HCLK_EMMC:
  144. con_id = 51;
  145. break;
  146. case SCLK_SDIO0:
  147. con_id = 48;
  148. break;
  149. default:
  150. return -EINVAL;
  151. }
  152. con = readl(&cru->clksel_con[con_id]);
  153. switch (con & MMC_PLL_SEL_MASK) {
  154. case MMC_PLL_SEL_GPLL:
  155. pll_rate = rkclk_pll_get_rate(cru, GPLL);
  156. break;
  157. case MMC_PLL_SEL_24M:
  158. pll_rate = OSC_HZ;
  159. break;
  160. case MMC_PLL_SEL_CPLL:
  161. pll_rate = rkclk_pll_get_rate(cru, CPLL);
  162. break;
  163. case MMC_PLL_SEL_USBPHY_480M:
  164. default:
  165. return -EINVAL;
  166. }
  167. div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
  168. rate = DIV_TO_RATE(pll_rate, div);
  169. debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
  170. return rate >> 1;
  171. }
  172. static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
  173. ulong rate,
  174. u32 *best_mux,
  175. u32 *best_div)
  176. {
  177. int i;
  178. ulong best_rate = 0;
  179. const ulong MHz = 1000000;
  180. const struct {
  181. u32 mux;
  182. ulong rate;
  183. } parents[] = {
  184. { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
  185. { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
  186. { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
  187. };
  188. debug("%s: target rate %ld\n", __func__, rate);
  189. for (i = 0; i < ARRAY_SIZE(parents); ++i) {
  190. /*
  191. * Find the largest rate no larger than the target-rate for
  192. * the current parent.
  193. */
  194. ulong parent_rate = parents[i].rate;
  195. u32 div = DIV_ROUND_UP(parent_rate, rate);
  196. u32 adj_div = div;
  197. ulong new_rate = parent_rate / adj_div;
  198. debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
  199. __func__, rate, parents[i].mux, parents[i].rate, div);
  200. /* Skip, if not representable */
  201. if ((div - 1) > MMC_CLK_DIV_MASK)
  202. continue;
  203. /* Skip, if we already have a better (or equal) solution */
  204. if (new_rate <= best_rate)
  205. continue;
  206. /* This is our new best rate. */
  207. best_rate = new_rate;
  208. *best_mux = parents[i].mux;
  209. *best_div = div - 1;
  210. }
  211. debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
  212. __func__, *best_mux, *best_div, best_rate);
  213. return best_rate;
  214. }
  215. static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
  216. {
  217. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  218. struct rk3368_cru *cru = priv->cru;
  219. ulong clk_id = clk->id;
  220. u32 con_id, mux = 0, div = 0;
  221. /* Find the best parent and rate */
  222. rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
  223. switch (clk_id) {
  224. case HCLK_SDMMC:
  225. con_id = 50;
  226. break;
  227. case HCLK_EMMC:
  228. con_id = 51;
  229. break;
  230. case SCLK_SDIO0:
  231. con_id = 48;
  232. break;
  233. default:
  234. return -EINVAL;
  235. }
  236. rk_clrsetreg(&cru->clksel_con[con_id],
  237. MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
  238. mux | div);
  239. return rk3368_mmc_get_clk(cru, clk_id);
  240. }
  241. #endif
  242. #if IS_ENABLED(CONFIG_TPL_BUILD)
  243. static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
  244. {
  245. const struct pll_div *dpll_cfg = NULL;
  246. const ulong MHz = 1000000;
  247. /* Fout = ((Fin /NR) * NF )/ NO */
  248. static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
  249. static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
  250. static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
  251. switch (set_rate) {
  252. case 1200*MHz:
  253. dpll_cfg = &dpll_1200;
  254. break;
  255. case 1332*MHz:
  256. dpll_cfg = &dpll_1332;
  257. break;
  258. case 1600*MHz:
  259. dpll_cfg = &dpll_1600;
  260. break;
  261. default:
  262. pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
  263. }
  264. rkclk_set_pll(cru, DPLL, dpll_cfg);
  265. return set_rate;
  266. }
  267. #endif
  268. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  269. static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate)
  270. {
  271. ulong ret;
  272. /*
  273. * The gmac clock can be derived either from an external clock
  274. * or can be generated from internally by a divider from SCLK_MAC.
  275. */
  276. if (readl(&cru->clksel_con[43]) & GMAC_MUX_SEL_EXTCLK) {
  277. /* An external clock will always generate the right rate... */
  278. ret = set_rate;
  279. } else {
  280. u32 con = readl(&cru->clksel_con[43]);
  281. ulong pll_rate;
  282. u8 div;
  283. if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  284. GMAC_PLL_SELECT_GENERAL)
  285. pll_rate = GPLL_HZ;
  286. else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
  287. GMAC_PLL_SELECT_CODEC)
  288. pll_rate = CPLL_HZ;
  289. else
  290. /* CPLL is not set */
  291. return -EPERM;
  292. div = DIV_ROUND_UP(pll_rate, set_rate) - 1;
  293. if (div <= 0x1f)
  294. rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK,
  295. div << GMAC_DIV_CON_SHIFT);
  296. else
  297. debug("Unsupported div for gmac:%d\n", div);
  298. return DIV_TO_RATE(pll_rate, div);
  299. }
  300. return ret;
  301. }
  302. #endif
  303. /*
  304. * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
  305. * to select either CPLL or GPLL as the clock-parent. The location within
  306. * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
  307. */
  308. struct spi_clkreg {
  309. uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
  310. uint8_t div_shift;
  311. uint8_t sel_shift;
  312. };
  313. /*
  314. * The entries are numbered relative to their offset from SCLK_SPI0.
  315. */
  316. static const struct spi_clkreg spi_clkregs[] = {
  317. [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
  318. [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
  319. [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
  320. };
  321. static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
  322. {
  323. return (val >> shift) & ((1 << width) - 1);
  324. }
  325. static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
  326. {
  327. const struct spi_clkreg *spiclk = NULL;
  328. u32 div, val;
  329. switch (clk_id) {
  330. case SCLK_SPI0 ... SCLK_SPI2:
  331. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  332. break;
  333. default:
  334. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  335. return -EINVAL;
  336. }
  337. val = readl(&cru->clksel_con[spiclk->reg]);
  338. div = extract_bits(val, 7, spiclk->div_shift);
  339. debug("%s: div 0x%x\n", __func__, div);
  340. return DIV_TO_RATE(GPLL_HZ, div);
  341. }
  342. static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
  343. {
  344. const struct spi_clkreg *spiclk = NULL;
  345. int src_clk_div;
  346. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
  347. assert(src_clk_div < 127);
  348. switch (clk_id) {
  349. case SCLK_SPI0 ... SCLK_SPI2:
  350. spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
  351. break;
  352. default:
  353. pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
  354. return -EINVAL;
  355. }
  356. rk_clrsetreg(&cru->clksel_con[spiclk->reg],
  357. ((0x7f << spiclk->div_shift) |
  358. (0x1 << spiclk->sel_shift)),
  359. ((src_clk_div << spiclk->div_shift) |
  360. (1 << spiclk->sel_shift)));
  361. return rk3368_spi_get_clk(cru, clk_id);
  362. }
  363. static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)
  364. {
  365. u32 div, val;
  366. val = readl(&cru->clksel_con[25]);
  367. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  368. CLK_SARADC_DIV_CON_WIDTH);
  369. return DIV_TO_RATE(OSC_HZ, div);
  370. }
  371. static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)
  372. {
  373. int src_clk_div;
  374. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  375. assert(src_clk_div < 128);
  376. rk_clrsetreg(&cru->clksel_con[25],
  377. CLK_SARADC_DIV_CON_MASK,
  378. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  379. return rk3368_saradc_get_clk(cru);
  380. }
  381. static ulong rk3368_clk_get_rate(struct clk *clk)
  382. {
  383. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  384. ulong rate = 0;
  385. debug("%s: id %ld\n", __func__, clk->id);
  386. switch (clk->id) {
  387. case PLL_CPLL:
  388. rate = rkclk_pll_get_rate(priv->cru, CPLL);
  389. break;
  390. case PLL_GPLL:
  391. rate = rkclk_pll_get_rate(priv->cru, GPLL);
  392. break;
  393. case SCLK_SPI0 ... SCLK_SPI2:
  394. rate = rk3368_spi_get_clk(priv->cru, clk->id);
  395. break;
  396. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  397. case HCLK_SDMMC:
  398. case HCLK_EMMC:
  399. rate = rk3368_mmc_get_clk(priv->cru, clk->id);
  400. break;
  401. #endif
  402. case SCLK_SARADC:
  403. rate = rk3368_saradc_get_clk(priv->cru);
  404. break;
  405. default:
  406. return -ENOENT;
  407. }
  408. return rate;
  409. }
  410. static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
  411. {
  412. __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  413. ulong ret = 0;
  414. debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
  415. switch (clk->id) {
  416. case SCLK_SPI0 ... SCLK_SPI2:
  417. ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
  418. break;
  419. #if IS_ENABLED(CONFIG_TPL_BUILD)
  420. case CLK_DDR:
  421. ret = rk3368_ddr_set_clk(priv->cru, rate);
  422. break;
  423. #endif
  424. #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
  425. case HCLK_SDMMC:
  426. case HCLK_EMMC:
  427. ret = rk3368_mmc_set_clk(clk, rate);
  428. break;
  429. #endif
  430. #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
  431. case SCLK_MAC:
  432. /* select the external clock */
  433. ret = rk3368_gmac_set_clk(priv->cru, rate);
  434. break;
  435. #endif
  436. case SCLK_SARADC:
  437. ret = rk3368_saradc_set_clk(priv->cru, rate);
  438. break;
  439. default:
  440. return -ENOENT;
  441. }
  442. return ret;
  443. }
  444. static int __maybe_unused rk3368_gmac_set_parent(struct clk *clk, struct clk *parent)
  445. {
  446. struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
  447. struct rk3368_cru *cru = priv->cru;
  448. const char *clock_output_name;
  449. int ret;
  450. /*
  451. * If the requested parent is in the same clock-controller and
  452. * the id is SCLK_MAC ("sclk_mac"), switch to the internal
  453. * clock.
  454. */
  455. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {
  456. debug("%s: switching GAMC to SCLK_MAC\n", __func__);
  457. rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  458. return 0;
  459. }
  460. /*
  461. * Otherwise, we need to check the clock-output-names of the
  462. * requested parent to see if the requested id is "ext_gmac".
  463. */
  464. ret = dev_read_string_index(parent->dev, "clock-output-names",
  465. parent->id, &clock_output_name);
  466. if (ret < 0)
  467. return -ENODATA;
  468. /* If this is "ext_gmac", switch to the external clock input */
  469. if (!strcmp(clock_output_name, "ext_gmac")) {
  470. debug("%s: switching GMAC to external clock\n", __func__);
  471. rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
  472. return 0;
  473. }
  474. return -EINVAL;
  475. }
  476. static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *parent)
  477. {
  478. switch (clk->id) {
  479. case SCLK_MAC:
  480. return rk3368_gmac_set_parent(clk, parent);
  481. }
  482. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  483. return -ENOENT;
  484. }
  485. static struct clk_ops rk3368_clk_ops = {
  486. .get_rate = rk3368_clk_get_rate,
  487. .set_rate = rk3368_clk_set_rate,
  488. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  489. .set_parent = rk3368_clk_set_parent,
  490. #endif
  491. };
  492. static int rk3368_clk_probe(struct udevice *dev)
  493. {
  494. struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
  495. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  496. struct rk3368_clk_plat *plat = dev_get_plat(dev);
  497. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  498. #endif
  499. #if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
  500. rkclk_init(priv->cru);
  501. #endif
  502. return 0;
  503. }
  504. static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
  505. {
  506. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  507. struct rk3368_clk_priv *priv = dev_get_priv(dev);
  508. priv->cru = dev_read_addr_ptr(dev);
  509. #endif
  510. return 0;
  511. }
  512. static int rk3368_clk_bind(struct udevice *dev)
  513. {
  514. int ret;
  515. struct udevice *sys_child;
  516. struct sysreset_reg *priv;
  517. /* The reset driver does not have a device node, so bind it here */
  518. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  519. &sys_child);
  520. if (ret) {
  521. debug("Warning: No sysreset driver: ret=%d\n", ret);
  522. } else {
  523. priv = malloc(sizeof(struct sysreset_reg));
  524. priv->glb_srst_fst_value = offsetof(struct rk3368_cru,
  525. glb_srst_fst_val);
  526. priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
  527. glb_srst_snd_val);
  528. sys_child->priv = priv;
  529. }
  530. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  531. ret = offsetof(struct rk3368_cru, softrst_con[0]);
  532. ret = rockchip_reset_bind(dev, ret, 15);
  533. if (ret)
  534. debug("Warning: software reset driver bind faile\n");
  535. #endif
  536. return ret;
  537. }
  538. static const struct udevice_id rk3368_clk_ids[] = {
  539. { .compatible = "rockchip,rk3368-cru" },
  540. { }
  541. };
  542. U_BOOT_DRIVER(rockchip_rk3368_cru) = {
  543. .name = "rockchip_rk3368_cru",
  544. .id = UCLASS_CLK,
  545. .of_match = rk3368_clk_ids,
  546. .priv_auto = sizeof(struct rk3368_clk_priv),
  547. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  548. .plat_auto = sizeof(struct rk3368_clk_plat),
  549. #endif
  550. .ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
  551. .ops = &rk3368_clk_ops,
  552. .bind = rk3368_clk_bind,
  553. .probe = rk3368_clk_probe,
  554. };