sata_mv.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, 2010.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
  7. */
  8. /*
  9. * This driver supports the SATA controller of some Mavell SoC's.
  10. * Here a (most likely incomplete) list of the supported SoC's:
  11. * - Kirkwood
  12. * - Armada 370
  13. * - Armada XP
  14. *
  15. * This driver implementation is an alternative to the already available
  16. * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
  17. * But this driver only supports PIO mode and as this new driver also
  18. * supports transfer via DMA, its much faster.
  19. *
  20. * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
  21. * by this driver. As they have an AHCI compatible SATA controller
  22. * integrated.
  23. */
  24. /*
  25. * TODO:
  26. * Better error recovery
  27. * No support for using PRDs (Thus max 64KB transfers)
  28. * No NCQ support
  29. * No port multiplier support
  30. */
  31. #include <common.h>
  32. #include <ahci.h>
  33. #include <blk.h>
  34. #include <cpu_func.h>
  35. #include <dm.h>
  36. #include <log.h>
  37. #include <asm/cache.h>
  38. #include <dm/device-internal.h>
  39. #include <dm/lists.h>
  40. #include <fis.h>
  41. #include <libata.h>
  42. #include <malloc.h>
  43. #include <sata.h>
  44. #include <linux/bitops.h>
  45. #include <linux/delay.h>
  46. #include <linux/errno.h>
  47. #include <asm/io.h>
  48. #include <linux/mbus.h>
  49. #include <asm/arch/soc.h>
  50. #if defined(CONFIG_ARCH_KIRKWOOD)
  51. #define SATAHC_BASE KW_SATA_BASE
  52. #else
  53. #define SATAHC_BASE MVEBU_AXP_SATA_BASE
  54. #endif
  55. #define SATA0_BASE (SATAHC_BASE + 0x2000)
  56. #define SATA1_BASE (SATAHC_BASE + 0x4000)
  57. /* EDMA registers */
  58. #define EDMA_CFG 0x000
  59. #define EDMA_CFG_NCQ (1 << 5)
  60. #define EDMA_CFG_EQUE (1 << 9)
  61. #define EDMA_TIMER 0x004
  62. #define EDMA_IECR 0x008
  63. #define EDMA_IEMR 0x00c
  64. #define EDMA_RQBA_HI 0x010
  65. #define EDMA_RQIPR 0x014
  66. #define EDMA_RQIPR_IPMASK (0x1f << 5)
  67. #define EDMA_RQIPR_IPSHIFT 5
  68. #define EDMA_RQOPR 0x018
  69. #define EDMA_RQOPR_OPMASK (0x1f << 5)
  70. #define EDMA_RQOPR_OPSHIFT 5
  71. #define EDMA_RSBA_HI 0x01c
  72. #define EDMA_RSIPR 0x020
  73. #define EDMA_RSIPR_IPMASK (0x1f << 3)
  74. #define EDMA_RSIPR_IPSHIFT 3
  75. #define EDMA_RSOPR 0x024
  76. #define EDMA_RSOPR_OPMASK (0x1f << 3)
  77. #define EDMA_RSOPR_OPSHIFT 3
  78. #define EDMA_CMD 0x028
  79. #define EDMA_CMD_ENEDMA (0x01 << 0)
  80. #define EDMA_CMD_DISEDMA (0x01 << 1)
  81. #define EDMA_CMD_ATARST (0x01 << 2)
  82. #define EDMA_CMD_FREEZE (0x01 << 4)
  83. #define EDMA_TEST_CTL 0x02c
  84. #define EDMA_STATUS 0x030
  85. #define EDMA_IORTO 0x034
  86. #define EDMA_CDTR 0x040
  87. #define EDMA_HLTCND 0x060
  88. #define EDMA_NTSR 0x094
  89. /* Basic DMA registers */
  90. #define BDMA_CMD 0x224
  91. #define BDMA_STATUS 0x228
  92. #define BDMA_DTLB 0x22c
  93. #define BDMA_DTHB 0x230
  94. #define BDMA_DRL 0x234
  95. #define BDMA_DRH 0x238
  96. /* SATA Interface registers */
  97. #define SIR_ICFG 0x050
  98. #define SIR_CFG_GEN2EN (0x1 << 7)
  99. #define SIR_PLL_CFG 0x054
  100. #define SIR_SSTATUS 0x300
  101. #define SSTATUS_DET_MASK (0x0f << 0)
  102. #define SIR_SERROR 0x304
  103. #define SIR_SCONTROL 0x308
  104. #define SIR_SCONTROL_DETEN (0x01 << 0)
  105. #define SIR_LTMODE 0x30c
  106. #define SIR_LTMODE_NELBE (0x01 << 7)
  107. #define SIR_PHYMODE3 0x310
  108. #define SIR_PHYMODE4 0x314
  109. #define SIR_PHYMODE1 0x32c
  110. #define SIR_PHYMODE2 0x330
  111. #define SIR_BIST_CTRL 0x334
  112. #define SIR_BIST_DW1 0x338
  113. #define SIR_BIST_DW2 0x33c
  114. #define SIR_SERR_IRQ_MASK 0x340
  115. #define SIR_SATA_IFCTRL 0x344
  116. #define SIR_SATA_TESTCTRL 0x348
  117. #define SIR_SATA_IFSTATUS 0x34c
  118. #define SIR_VEND_UNIQ 0x35c
  119. #define SIR_FIS_CFG 0x360
  120. #define SIR_FIS_IRQ_CAUSE 0x364
  121. #define SIR_FIS_IRQ_MASK 0x368
  122. #define SIR_FIS_DWORD0 0x370
  123. #define SIR_FIS_DWORD1 0x374
  124. #define SIR_FIS_DWORD2 0x378
  125. #define SIR_FIS_DWORD3 0x37c
  126. #define SIR_FIS_DWORD4 0x380
  127. #define SIR_FIS_DWORD5 0x384
  128. #define SIR_FIS_DWORD6 0x388
  129. #define SIR_PHYM9_GEN2 0x398
  130. #define SIR_PHYM9_GEN1 0x39c
  131. #define SIR_PHY_CFG 0x3a0
  132. #define SIR_PHYCTL 0x3a4
  133. #define SIR_PHYM10 0x3a8
  134. #define SIR_PHYM12 0x3b0
  135. /* Shadow registers */
  136. #define PIO_DATA 0x100
  137. #define PIO_ERR_FEATURES 0x104
  138. #define PIO_SECTOR_COUNT 0x108
  139. #define PIO_LBA_LOW 0x10c
  140. #define PIO_LBA_MID 0x110
  141. #define PIO_LBA_HI 0x114
  142. #define PIO_DEVICE 0x118
  143. #define PIO_CMD_STATUS 0x11c
  144. #define PIO_STATUS_ERR (0x01 << 0)
  145. #define PIO_STATUS_DRQ (0x01 << 3)
  146. #define PIO_STATUS_DF (0x01 << 5)
  147. #define PIO_STATUS_DRDY (0x01 << 6)
  148. #define PIO_STATUS_BSY (0x01 << 7)
  149. #define PIO_CTRL_ALTSTAT 0x120
  150. /* SATAHC arbiter registers */
  151. #define SATAHC_CFG 0x000
  152. #define SATAHC_RQOP 0x004
  153. #define SATAHC_RQIP 0x008
  154. #define SATAHC_ICT 0x00c
  155. #define SATAHC_ITT 0x010
  156. #define SATAHC_ICR 0x014
  157. #define SATAHC_ICR_PORT0 (0x01 << 0)
  158. #define SATAHC_ICR_PORT1 (0x01 << 1)
  159. #define SATAHC_MIC 0x020
  160. #define SATAHC_MIM 0x024
  161. #define SATAHC_LED_CFG 0x02c
  162. #define REQUEST_QUEUE_SIZE 32
  163. #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
  164. struct crqb {
  165. u32 dtb_low; /* DW0 */
  166. u32 dtb_high; /* DW1 */
  167. u32 control_flags; /* DW2 */
  168. u32 drb_count; /* DW3 */
  169. u32 ata_cmd_feat; /* DW4 */
  170. u32 ata_addr; /* DW5 */
  171. u32 ata_addr_exp; /* DW6 */
  172. u32 ata_sect_count; /* DW7 */
  173. };
  174. #define CRQB_ALIGN 0x400
  175. #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
  176. #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
  177. #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
  178. #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
  179. #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
  180. #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
  181. #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
  182. #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
  183. #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
  184. #define CRQB_CMDFEAT_CMDSHIFT 16
  185. #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
  186. #define CRQB_CMDFEAT_FEATSHIFT 24
  187. #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
  188. #define CRQB_ADDR_LBA_LOWSHIFT 0
  189. #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
  190. #define CRQB_ADDR_LBA_MIDSHIFT 8
  191. #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
  192. #define CRQB_ADDR_LBA_HIGHSHIFT 16
  193. #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
  194. #define CRQB_ADDR_DEVICE_SHIFT 24
  195. #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
  196. #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
  197. #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
  198. #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
  199. #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
  200. #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
  201. #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
  202. #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
  203. #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
  204. #define CRQB_SECTCOUNT_COUNT_SHIFT 0
  205. #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
  206. #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
  207. #define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
  208. #define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
  209. struct eprd {
  210. u32 phyaddr_low;
  211. u32 bytecount_eot;
  212. u32 phyaddr_hi;
  213. u32 reserved;
  214. };
  215. #define EPRD_PHYADDR_MASK 0xfffffffe
  216. #define EPRD_BYTECOUNT_MASK 0x0000ffff
  217. #define EPRD_EOT (0x01 << 31)
  218. struct crpb {
  219. u32 id;
  220. u32 flags;
  221. u32 timestamp;
  222. };
  223. #define CRPB_ALIGN 0x100
  224. #define READ_CMD 0
  225. #define WRITE_CMD 1
  226. /*
  227. * Since we don't use PRDs yet max transfer size
  228. * is 64KB
  229. */
  230. #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
  231. /* Keep track if hw is initialized or not */
  232. static u32 hw_init;
  233. struct mv_priv {
  234. char name[12];
  235. u32 link;
  236. u32 regbase;
  237. u32 queue_depth;
  238. u16 pio;
  239. u16 mwdma;
  240. u16 udma;
  241. int dev_nr;
  242. void *crqb_alloc;
  243. struct crqb *request;
  244. void *crpb_alloc;
  245. struct crpb *response;
  246. };
  247. static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
  248. {
  249. ulong start;
  250. start = get_timer(0);
  251. do {
  252. if ((in_le32(addr) & mask) == val)
  253. return 0;
  254. } while (get_timer(start) < timeout_msec);
  255. return -ETIMEDOUT;
  256. }
  257. /* Cut from sata_mv in linux kernel */
  258. static int mv_stop_edma_engine(struct udevice *dev, int port)
  259. {
  260. struct mv_priv *priv = dev_get_plat(dev);
  261. int i;
  262. /* Disable eDMA. The disable bit auto clears. */
  263. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
  264. /* Wait for the chip to confirm eDMA is off. */
  265. for (i = 10000; i > 0; i--) {
  266. u32 reg = in_le32(priv->regbase + EDMA_CMD);
  267. if (!(reg & EDMA_CMD_ENEDMA)) {
  268. debug("EDMA stop on port %d succesful\n", port);
  269. return 0;
  270. }
  271. udelay(10);
  272. }
  273. debug("EDMA stop on port %d failed\n", port);
  274. return -1;
  275. }
  276. static int mv_start_edma_engine(struct udevice *dev, int port)
  277. {
  278. struct mv_priv *priv = dev_get_plat(dev);
  279. u32 tmp;
  280. /* Check preconditions */
  281. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  282. if ((tmp & SSTATUS_DET_MASK) != 0x03) {
  283. printf("Device error on port: %d\n", port);
  284. return -1;
  285. }
  286. tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
  287. if (tmp & (ATA_BUSY | ATA_DRQ)) {
  288. printf("Device not ready on port: %d\n", port);
  289. return -1;
  290. }
  291. /* Clear interrupt cause */
  292. out_le32(priv->regbase + EDMA_IECR, 0x0);
  293. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  294. tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
  295. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  296. /* Configure edma operation */
  297. tmp = in_le32(priv->regbase + EDMA_CFG);
  298. tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
  299. tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
  300. out_le32(priv->regbase + EDMA_CFG, tmp);
  301. out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
  302. /* Configure fis, set all to no-wait for now */
  303. out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
  304. /* Setup request queue */
  305. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  306. out_le32(priv->regbase + EDMA_RQIPR, priv->request);
  307. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  308. /* Setup response queue */
  309. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  310. out_le32(priv->regbase + EDMA_RSOPR, priv->response);
  311. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  312. /* Start edma */
  313. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
  314. return 0;
  315. }
  316. static int mv_reset_channel(struct udevice *dev, int port)
  317. {
  318. struct mv_priv *priv = dev_get_plat(dev);
  319. /* Make sure edma is stopped */
  320. mv_stop_edma_engine(dev, port);
  321. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
  322. udelay(25); /* allow reset propagation */
  323. out_le32(priv->regbase + EDMA_CMD, 0);
  324. mdelay(10);
  325. return 0;
  326. }
  327. static void mv_reset_port(struct udevice *dev, int port)
  328. {
  329. struct mv_priv *priv = dev_get_plat(dev);
  330. mv_reset_channel(dev, port);
  331. out_le32(priv->regbase + EDMA_CMD, 0x0);
  332. out_le32(priv->regbase + EDMA_CFG, 0x101f);
  333. out_le32(priv->regbase + EDMA_IECR, 0x0);
  334. out_le32(priv->regbase + EDMA_IEMR, 0x0);
  335. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  336. out_le32(priv->regbase + EDMA_RQIPR, 0x0);
  337. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  338. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  339. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  340. out_le32(priv->regbase + EDMA_RSOPR, 0x0);
  341. out_le32(priv->regbase + EDMA_IORTO, 0xfa);
  342. }
  343. static void mv_reset_one_hc(void)
  344. {
  345. out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
  346. out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
  347. out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
  348. }
  349. static int probe_port(struct udevice *dev, int port)
  350. {
  351. struct mv_priv *priv = dev_get_plat(dev);
  352. int tries, tries2, set15 = 0;
  353. u32 tmp;
  354. debug("Probe port: %d\n", port);
  355. for (tries = 0; tries < 2; tries++) {
  356. /* Clear SError */
  357. out_le32(priv->regbase + SIR_SERROR, 0x0);
  358. /* trigger com-init */
  359. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  360. tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
  361. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  362. mdelay(1);
  363. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  364. tries2 = 5;
  365. do {
  366. tmp = (tmp & 0x0f0) | 0x300;
  367. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  368. mdelay(10);
  369. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  370. } while ((tmp & 0xf0f) != 0x300 && tries2--);
  371. mdelay(10);
  372. for (tries2 = 0; tries2 < 200; tries2++) {
  373. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  374. if ((tmp & SSTATUS_DET_MASK) == 0x03) {
  375. debug("Found device on port\n");
  376. return 0;
  377. }
  378. mdelay(1);
  379. }
  380. if ((tmp & SSTATUS_DET_MASK) == 0) {
  381. debug("No device attached on port %d\n", port);
  382. return -ENODEV;
  383. }
  384. if (!set15) {
  385. /* Try on 1.5Gb/S */
  386. debug("Try 1.5Gb link\n");
  387. set15 = 1;
  388. out_le32(priv->regbase + SIR_SCONTROL, 0x304);
  389. tmp = in_le32(priv->regbase + SIR_ICFG);
  390. tmp &= ~SIR_CFG_GEN2EN;
  391. out_le32(priv->regbase + SIR_ICFG, tmp);
  392. mv_reset_channel(dev, port);
  393. }
  394. }
  395. debug("Failed to probe port\n");
  396. return -1;
  397. }
  398. /* Get request queue in pointer */
  399. static int get_reqip(struct udevice *dev, int port)
  400. {
  401. struct mv_priv *priv = dev_get_plat(dev);
  402. u32 tmp;
  403. tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
  404. tmp = tmp >> EDMA_RQIPR_IPSHIFT;
  405. return tmp;
  406. }
  407. static void set_reqip(struct udevice *dev, int port, int reqin)
  408. {
  409. struct mv_priv *priv = dev_get_plat(dev);
  410. u32 tmp;
  411. tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
  412. tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
  413. out_le32(priv->regbase + EDMA_RQIPR, tmp);
  414. }
  415. /* Get next available slot, ignoring possible overwrite */
  416. static int get_next_reqip(struct udevice *dev, int port)
  417. {
  418. int slot = get_reqip(dev, port);
  419. slot = (slot + 1) % REQUEST_QUEUE_SIZE;
  420. return slot;
  421. }
  422. /* Get response queue in pointer */
  423. static int get_rspip(struct udevice *dev, int port)
  424. {
  425. struct mv_priv *priv = dev_get_plat(dev);
  426. u32 tmp;
  427. tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
  428. tmp = tmp >> EDMA_RSIPR_IPSHIFT;
  429. return tmp;
  430. }
  431. /* Get response queue out pointer */
  432. static int get_rspop(struct udevice *dev, int port)
  433. {
  434. struct mv_priv *priv = dev_get_plat(dev);
  435. u32 tmp;
  436. tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
  437. tmp = tmp >> EDMA_RSOPR_OPSHIFT;
  438. return tmp;
  439. }
  440. /* Get next response queue pointer */
  441. static int get_next_rspop(struct udevice *dev, int port)
  442. {
  443. return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
  444. }
  445. /* Set response queue pointer */
  446. static void set_rspop(struct udevice *dev, int port, int reqin)
  447. {
  448. struct mv_priv *priv = dev_get_plat(dev);
  449. u32 tmp;
  450. tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
  451. tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
  452. out_le32(priv->regbase + EDMA_RSOPR, tmp);
  453. }
  454. static int wait_dma_completion(struct udevice *dev, int port, int index,
  455. u32 timeout_msec)
  456. {
  457. u32 tmp, res;
  458. tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
  459. res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
  460. tmp, timeout_msec);
  461. if (res)
  462. printf("Failed to wait for completion on port %d\n", port);
  463. return res;
  464. }
  465. static void process_responses(struct udevice *dev, int port)
  466. {
  467. #ifdef DEBUG
  468. struct mv_priv *priv = dev_get_plat(dev);
  469. #endif
  470. u32 tmp;
  471. u32 outind = get_rspop(dev, port);
  472. /* Ack interrupts */
  473. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  474. if (port == 0)
  475. tmp &= ~(BIT(0) | BIT(8));
  476. else
  477. tmp &= ~(BIT(1) | BIT(9));
  478. tmp &= ~(BIT(4));
  479. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  480. while (get_rspip(dev, port) != outind) {
  481. #ifdef DEBUG
  482. debug("Response index %d flags %08x on port %d\n", outind,
  483. priv->response[outind].flags, port);
  484. #endif
  485. outind = get_next_rspop(dev, port);
  486. set_rspop(dev, port, outind);
  487. }
  488. }
  489. static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
  490. struct sata_fis_h2d *cfis,
  491. u8 *buffer, u32 len, u32 iswrite)
  492. {
  493. struct mv_priv *priv = dev_get_plat(dev);
  494. struct crqb *req;
  495. int slot;
  496. u32 start;
  497. if (len >= 64 * 1024) {
  498. printf("We only support <64K transfers for now\n");
  499. return -1;
  500. }
  501. /* Initialize request */
  502. slot = get_reqip(dev, port);
  503. memset(&priv->request[slot], 0, sizeof(struct crqb));
  504. req = &priv->request[slot];
  505. req->dtb_low = (u32)buffer;
  506. /* Dont use PRDs */
  507. req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
  508. req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
  509. req->control_flags |=
  510. ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
  511. & CRQB_CNTRLFLAGS_PMPORTMASK);
  512. req->drb_count = len;
  513. req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
  514. CRQB_CMDFEAT_CMDMASK;
  515. req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
  516. CRQB_CMDFEAT_FEATMASK;
  517. req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
  518. CRQB_ADDR_LBA_LOWMASK;
  519. req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
  520. CRQB_ADDR_LBA_MIDMASK;
  521. req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
  522. CRQB_ADDR_LBA_HIGHMASK;
  523. req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
  524. CRQB_ADDR_DEVICE_MASK;
  525. req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
  526. CRQB_ADDR_LBA_LOW_EXP_MASK;
  527. req->ata_addr_exp |=
  528. (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
  529. CRQB_ADDR_LBA_MID_EXP_MASK;
  530. req->ata_addr_exp |=
  531. (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
  532. CRQB_ADDR_LBA_HIGH_EXP_MASK;
  533. req->ata_addr_exp |=
  534. (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
  535. CRQB_ADDR_FEATURE_EXP_MASK;
  536. req->ata_sect_count =
  537. (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
  538. CRQB_SECTCOUNT_COUNT_MASK;
  539. req->ata_sect_count |=
  540. (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
  541. CRQB_SECTCOUNT_COUNT_EXP_MASK;
  542. /* Flush data */
  543. start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
  544. flush_dcache_range(start,
  545. start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
  546. /* Trigger operation */
  547. slot = get_next_reqip(dev, port);
  548. set_reqip(dev, port, slot);
  549. /* Wait for completion */
  550. if (wait_dma_completion(dev, port, slot, 10000)) {
  551. printf("ATA operation timed out\n");
  552. return -1;
  553. }
  554. process_responses(dev, port);
  555. /* Invalidate data on read */
  556. if (buffer && len) {
  557. start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
  558. invalidate_dcache_range(start,
  559. start + ALIGN(len, ARCH_DMA_MINALIGN));
  560. }
  561. return len;
  562. }
  563. static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
  564. u32 blkcnt,
  565. u8 *buffer, int is_write)
  566. {
  567. struct sata_fis_h2d cfis;
  568. u32 res;
  569. u64 block;
  570. block = (u64)start;
  571. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  572. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  573. cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  574. cfis.lba_high_exp = (block >> 40) & 0xff;
  575. cfis.lba_mid_exp = (block >> 32) & 0xff;
  576. cfis.lba_low_exp = (block >> 24) & 0xff;
  577. cfis.lba_high = (block >> 16) & 0xff;
  578. cfis.lba_mid = (block >> 8) & 0xff;
  579. cfis.lba_low = block & 0xff;
  580. cfis.device = ATA_LBA;
  581. cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
  582. cfis.sector_count = blkcnt & 0xff;
  583. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  584. ATA_SECT_SIZE * blkcnt, is_write);
  585. return res >= 0 ? blkcnt : res;
  586. }
  587. static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
  588. u32 blkcnt, u8 *buffer, int is_write)
  589. {
  590. struct sata_fis_h2d cfis;
  591. lbaint_t block;
  592. u32 res;
  593. block = start;
  594. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  595. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  596. cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  597. cfis.device = ATA_LBA;
  598. cfis.device |= (block >> 24) & 0xf;
  599. cfis.lba_high = (block >> 16) & 0xff;
  600. cfis.lba_mid = (block >> 8) & 0xff;
  601. cfis.lba_low = block & 0xff;
  602. cfis.sector_count = (u8)(blkcnt & 0xff);
  603. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  604. ATA_SECT_SIZE * blkcnt, is_write);
  605. return res >= 0 ? blkcnt : res;
  606. }
  607. static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
  608. lbaint_t blkcnt, void *buffer, int is_write)
  609. {
  610. struct blk_desc *desc = dev_get_uclass_plat(dev);
  611. lbaint_t start, blks;
  612. u8 *addr;
  613. int max_blks;
  614. debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
  615. start = blknr;
  616. blks = blkcnt;
  617. addr = (u8 *)buffer;
  618. max_blks = MV_ATA_MAX_SECTORS;
  619. do {
  620. if (blks > max_blks) {
  621. if (desc->lba48) {
  622. mv_sata_rw_cmd_ext(dev, port, start, max_blks,
  623. addr, is_write);
  624. } else {
  625. mv_sata_rw_cmd(dev, port, start, max_blks,
  626. addr, is_write);
  627. }
  628. start += max_blks;
  629. blks -= max_blks;
  630. addr += ATA_SECT_SIZE * max_blks;
  631. } else {
  632. if (desc->lba48) {
  633. mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
  634. is_write);
  635. } else {
  636. mv_sata_rw_cmd(dev, port, start, blks, addr,
  637. is_write);
  638. }
  639. start += blks;
  640. blks = 0;
  641. addr += ATA_SECT_SIZE * blks;
  642. }
  643. } while (blks != 0);
  644. return blkcnt;
  645. }
  646. static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
  647. struct sata_fis_h2d *cfis, u8 *buffer,
  648. u32 len, u32 iswrite)
  649. {
  650. struct mv_priv *priv = dev_get_plat(dev);
  651. int i;
  652. u16 *tp;
  653. debug("%s\n", __func__);
  654. out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
  655. out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
  656. out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
  657. out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
  658. out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
  659. out_le32(priv->regbase + PIO_DEVICE, cfis->device);
  660. out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
  661. if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
  662. ATA_BUSY, 0x0, 10000)) {
  663. debug("Failed to wait for completion\n");
  664. return -1;
  665. }
  666. if (len > 0) {
  667. tp = (u16 *)buffer;
  668. for (i = 0; i < len / 2; i++) {
  669. if (iswrite)
  670. out_le16(priv->regbase + PIO_DATA, *tp++);
  671. else
  672. *tp++ = in_le16(priv->regbase + PIO_DATA);
  673. }
  674. }
  675. return len;
  676. }
  677. static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
  678. {
  679. struct sata_fis_h2d h2d;
  680. memset(&h2d, 0, sizeof(struct sata_fis_h2d));
  681. h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  682. h2d.command = ATA_CMD_ID_ATA;
  683. /* Give device time to get operational */
  684. mdelay(10);
  685. return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
  686. ATA_ID_WORDS * 2, READ_CMD);
  687. }
  688. static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
  689. {
  690. struct mv_priv *priv = dev_get_plat(dev);
  691. priv->pio = id[ATA_ID_PIO_MODES];
  692. priv->mwdma = id[ATA_ID_MWDMA_MODES];
  693. priv->udma = id[ATA_ID_UDMA_MODES];
  694. debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
  695. priv->udma);
  696. }
  697. static void mv_sata_set_features(struct udevice *dev, int port)
  698. {
  699. struct mv_priv *priv = dev_get_plat(dev);
  700. struct sata_fis_h2d cfis;
  701. u8 udma_cap;
  702. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  703. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  704. cfis.command = ATA_CMD_SET_FEATURES;
  705. cfis.features = SETFEATURES_XFER;
  706. /* First check the device capablity */
  707. udma_cap = (u8) (priv->udma & 0xff);
  708. if (udma_cap == ATA_UDMA6)
  709. cfis.sector_count = XFER_UDMA_6;
  710. if (udma_cap == ATA_UDMA5)
  711. cfis.sector_count = XFER_UDMA_5;
  712. if (udma_cap == ATA_UDMA4)
  713. cfis.sector_count = XFER_UDMA_4;
  714. if (udma_cap == ATA_UDMA3)
  715. cfis.sector_count = XFER_UDMA_3;
  716. mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
  717. }
  718. /*
  719. * Initialize SATA memory windows
  720. */
  721. static void mvsata_ide_conf_mbus_windows(void)
  722. {
  723. const struct mbus_dram_target_info *dram;
  724. int i;
  725. dram = mvebu_mbus_dram_info();
  726. /* Disable windows, Set Size/Base to 0 */
  727. for (i = 0; i < 4; i++) {
  728. writel(0, MVSATA_WIN_CONTROL(i));
  729. writel(0, MVSATA_WIN_BASE(i));
  730. }
  731. for (i = 0; i < dram->num_cs; i++) {
  732. const struct mbus_dram_window *cs = dram->cs + i;
  733. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  734. (dram->mbus_dram_target_id << 4) | 1,
  735. MVSATA_WIN_CONTROL(i));
  736. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  737. }
  738. }
  739. static int sata_mv_init_sata(struct udevice *dev, int port)
  740. {
  741. struct mv_priv *priv = dev_get_plat(dev);
  742. debug("Initialize sata dev: %d\n", port);
  743. if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
  744. printf("Invalid sata device %d\n", port);
  745. return -1;
  746. }
  747. /* Allocate and align request buffer */
  748. priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
  749. CRQB_ALIGN);
  750. if (!priv->crqb_alloc) {
  751. printf("Unable to allocate memory for request queue\n");
  752. return -ENOMEM;
  753. }
  754. memset(priv->crqb_alloc, 0,
  755. sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
  756. priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
  757. ~(CRQB_ALIGN - 1));
  758. /* Allocate and align response buffer */
  759. priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
  760. CRPB_ALIGN);
  761. if (!priv->crpb_alloc) {
  762. printf("Unable to allocate memory for response queue\n");
  763. return -ENOMEM;
  764. }
  765. memset(priv->crpb_alloc, 0,
  766. sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
  767. priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
  768. ~(CRPB_ALIGN - 1));
  769. sprintf(priv->name, "SATA%d", port);
  770. priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
  771. if (!hw_init) {
  772. debug("Initialize sata hw\n");
  773. hw_init = 1;
  774. mv_reset_one_hc();
  775. mvsata_ide_conf_mbus_windows();
  776. }
  777. mv_reset_port(dev, port);
  778. if (probe_port(dev, port)) {
  779. priv->link = 0;
  780. return -ENODEV;
  781. }
  782. priv->link = 1;
  783. return 0;
  784. }
  785. static int sata_mv_scan_sata(struct udevice *dev, int port)
  786. {
  787. struct blk_desc *desc = dev_get_uclass_plat(dev);
  788. struct mv_priv *priv = dev_get_plat(dev);
  789. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  790. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  791. unsigned char product[ATA_ID_PROD_LEN + 1];
  792. u64 n_sectors;
  793. u16 *id;
  794. if (!priv->link)
  795. return -ENODEV;
  796. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  797. if (!id) {
  798. printf("Failed to malloc id data\n");
  799. return -ENOMEM;
  800. }
  801. mv_sata_identify(dev, port, id);
  802. ata_swap_buf_le16(id, ATA_ID_WORDS);
  803. #ifdef DEBUG
  804. ata_dump_id(id);
  805. #endif
  806. /* Serial number */
  807. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  808. memcpy(desc->product, serial, sizeof(serial));
  809. /* Firmware version */
  810. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  811. memcpy(desc->revision, firmware, sizeof(firmware));
  812. /* Product model */
  813. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  814. memcpy(desc->vendor, product, sizeof(product));
  815. /* Total sectors */
  816. n_sectors = ata_id_n_sectors(id);
  817. desc->lba = n_sectors;
  818. /* Check if support LBA48 */
  819. if (ata_id_has_lba48(id)) {
  820. desc->lba48 = 1;
  821. debug("Device support LBA48\n");
  822. }
  823. /* Get the NCQ queue depth from device */
  824. priv->queue_depth = ata_id_queue_depth(id);
  825. /* Get the xfer mode from device */
  826. mv_sata_xfer_mode(dev, port, id);
  827. /* Set the xfer mode to highest speed */
  828. mv_sata_set_features(dev, port);
  829. /* Start up */
  830. mv_start_edma_engine(dev, port);
  831. return 0;
  832. }
  833. static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
  834. lbaint_t blkcnt, void *buffer)
  835. {
  836. struct mv_priv *priv = dev_get_plat(blk);
  837. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  838. buffer, READ_CMD);
  839. }
  840. static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
  841. lbaint_t blkcnt, const void *buffer)
  842. {
  843. struct mv_priv *priv = dev_get_plat(blk);
  844. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  845. (void *)buffer, WRITE_CMD);
  846. }
  847. static const struct blk_ops sata_mv_blk_ops = {
  848. .read = sata_mv_read,
  849. .write = sata_mv_write,
  850. };
  851. U_BOOT_DRIVER(sata_mv_driver) = {
  852. .name = "sata_mv_blk",
  853. .id = UCLASS_BLK,
  854. .ops = &sata_mv_blk_ops,
  855. .plat_auto = sizeof(struct mv_priv),
  856. };
  857. static int sata_mv_probe(struct udevice *dev)
  858. {
  859. const void *blob = gd->fdt_blob;
  860. int node = dev_of_offset(dev);
  861. struct mv_priv *priv;
  862. struct udevice *blk;
  863. int nr_ports;
  864. int ret;
  865. int i;
  866. /* Get number of ports of this SATA controller */
  867. nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
  868. CONFIG_SYS_SATA_MAX_DEVICE);
  869. for (i = 0; i < nr_ports; i++) {
  870. ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
  871. IF_TYPE_SATA, -1, 512, 0, &blk);
  872. if (ret) {
  873. debug("Can't create device\n");
  874. return ret;
  875. }
  876. priv = dev_get_plat(blk);
  877. priv->dev_nr = i;
  878. /* Init SATA port */
  879. ret = sata_mv_init_sata(blk, i);
  880. if (ret) {
  881. debug("%s: Failed to init bus\n", __func__);
  882. return ret;
  883. }
  884. /* Scan SATA port */
  885. ret = sata_mv_scan_sata(blk, i);
  886. if (ret) {
  887. debug("%s: Failed to scan bus\n", __func__);
  888. return ret;
  889. }
  890. }
  891. return 0;
  892. }
  893. static int sata_mv_scan(struct udevice *dev)
  894. {
  895. /* Nothing to do here */
  896. return 0;
  897. }
  898. static const struct udevice_id sata_mv_ids[] = {
  899. { .compatible = "marvell,armada-370-sata" },
  900. { .compatible = "marvell,orion-sata" },
  901. { }
  902. };
  903. struct ahci_ops sata_mv_ahci_ops = {
  904. .scan = sata_mv_scan,
  905. };
  906. U_BOOT_DRIVER(sata_mv_ahci) = {
  907. .name = "sata_mv_ahci",
  908. .id = UCLASS_AHCI,
  909. .of_match = sata_mv_ids,
  910. .ops = &sata_mv_ahci_ops,
  911. .probe = sata_mv_probe,
  912. };