mt7620-eth.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <clk.h>
  10. #include <malloc.h>
  11. #include <miiphy.h>
  12. #include <misc.h>
  13. #include <net.h>
  14. #include <reset.h>
  15. #include <asm/addrspace.h>
  16. #include <asm/cache.h>
  17. #include <asm/gpio.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/bitfield.h>
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/err.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/io.h>
  25. #include <linux/iopoll.h>
  26. #include <linux/mdio.h>
  27. #include <linux/mii.h>
  28. #include <mach/mt7620-sysc.h>
  29. /* Frame Engine block */
  30. #define GDMA_BASE 0x600
  31. #define PDMA_BASE 0x800
  32. /* GDMA registers */
  33. #define GDMA_FWD_CFG 0x00
  34. #define GDMA_DST_PORT GENMASK(2, 0)
  35. #define GDMA_DST_PORT_CPU 0
  36. #define GDMA_MAC_ADRL 0x08
  37. #define GDMA_MAC_ADRH 0x0c
  38. /* PDMA registers */
  39. #define TX_BASE_PTR0 0x000
  40. #define TX_MAX_CNT0 0x004
  41. #define TX_CTX_IDX0 0x008
  42. #define TX_DTX_IDX0 0x00c
  43. #define RX_BASE_PTR0 0x100
  44. #define RX_MAX_CNT0 0x104
  45. #define RX_CALC_IDX0 0x108
  46. #define RX_DRX_IDX0 0x10c
  47. #define PDMA_GLO_CFG 0x204
  48. #define TX_WB_DDONE BIT(6)
  49. #define PDMA_BT_SIZE GENMASK(5, 4)
  50. #define PDMA_BT_SIZE_32B 1
  51. #define RX_DMA_BUSY BIT(3)
  52. #define RX_DMA_EN BIT(2)
  53. #define TX_DMA_BUSY BIT(1)
  54. #define TX_DMA_EN BIT(0)
  55. #define PDMA_RST_IDX 0x208
  56. #define RST_DRX_IDX0 BIT(16)
  57. #define RST_DTX_IDX0 BIT(0)
  58. /* Built-in giga ethernet switch block */
  59. /* ARL registers */
  60. #define GSW_MFC 0x0010
  61. #define BC_FFP GENMASK(31, 24)
  62. #define UNM_FFP GENMASK(23, 16)
  63. #define UNU_FFP GENMASK(15, 8)
  64. #define CPU_EN BIT(7)
  65. #define CPU_PORT GENMASK(6, 4)
  66. /* Port registers */
  67. #define GSW_PCR(p) (0x2004 + (p) * 0x100)
  68. #define PORT_MATRIX GENMASK(23, 16)
  69. #define GSW_PVC(p) (0x2010 + (p) * 0x100)
  70. #define STAG_VPID GENMASK(31, 16)
  71. #define VLAN_ATTR GENMASK(7, 6)
  72. #define VLAN_ATTR_USER 0
  73. /* MAC registers */
  74. #define GSW_PMCR(p) (0x3000 + (p) * 0x100)
  75. #define IPG_CFG GENMASK(19, 18)
  76. #define IPG_96BIT_WITH_SHORT_IPG 1
  77. #define MAC_MODE BIT(16)
  78. #define FORCE_MODE BIT(15)
  79. #define MAC_TX_EN BIT(14)
  80. #define MAC_RX_EN BIT(13)
  81. #define BKOFF_EN BIT(9)
  82. #define BACKPR_EN BIT(8)
  83. #define FORCE_EEE1G BIT(7)
  84. #define FORCE_EEE100 BIT(6)
  85. #define FORCE_RX_FC BIT(5)
  86. #define FORCE_TX_FC BIT(4)
  87. #define FORCE_SPEED GENMASK(3, 2)
  88. #define FORCE_SPEED_1000 2
  89. #define FORCE_SPEED_100 1
  90. #define FORCE_SPEED_10 0
  91. #define FORCE_DUPLEX BIT(1)
  92. #define FORCE_LINK BIT(0)
  93. /* GMAC registers */
  94. #define GSW_PPSC 0x7000
  95. #define PHY_AP_EN BIT(31)
  96. #define PHY_PRE_EN BIT(30)
  97. #define PHY_MDC_CFG GENMASK(29, 24)
  98. #define EPHY_AP_EN BIT(23)
  99. #define EE_AN_EN BIT(16)
  100. #define PHY_AP_END_ADDR GENMASK(12, 8)
  101. #define PHY_AP_START_ADDR GENMASK(4, 0)
  102. #define GSW_PIAC 0x7004
  103. #define PHY_ACS_ST BIT(31)
  104. #define MDIO_REG_ADDR GENMASK(29, 25)
  105. #define MDIO_PHY_ADDR GENMASK(24, 20)
  106. #define MDIO_CMD GENMASK(19, 18)
  107. #define MDIO_CMD_WRITE 1
  108. #define MDIO_CMD_READ 2
  109. #define MDIO_ST GENMASK(17, 16)
  110. #define MDIO_RW_DATA GENMASK(15, 0)
  111. #define GSW_GPC1 0x7014
  112. #define PHY_DIS GENMASK(28, 24)
  113. #define PHY_BASE GENMASK(20, 16)
  114. #define TX_CLK_MODE BIT(3)
  115. #define RX_CLK_MODE BIT(2)
  116. /* MII Registers for MDIO clause 45 indirect access */
  117. #define MII_MMD_ACC_CTL_REG 0x0d
  118. #define MMD_OP_MODE GENMASK(15, 14)
  119. #define MMD_ADDR 0
  120. #define MMD_DATA 1
  121. #define MMD_DATA_RW_POST_INC 2
  122. #define MMD_DATA_W_POST_INC 3
  123. #define MMD_DEVAD GENMASK(4, 0)
  124. #define MII_MMD_ADDR_DATA_REG 0x0e
  125. /* MT7530 internal register access */
  126. #define MT7530_REG_PAGE_ADDR GENMASK(15, 6)
  127. #define MT7530_REG_ADDR GENMASK(5, 2)
  128. /* MT7530 system control registers*/
  129. #define MT7530_SYS_CTRL 0x7000
  130. #define SW_SYS_RST BIT(1)
  131. #define SW_REG_RST BIT(0)
  132. #define MT7530_MHWTRAP 0x7804
  133. #define P5_INTF_SEL_GMAC5 BIT(13)
  134. #define P5_INTF_DIS BIT(6)
  135. struct pdma_txd_info1 {
  136. u32 SDP0;
  137. };
  138. struct pdma_txd_info2 {
  139. u32 SDL1 : 14;
  140. u32 LS1 : 1;
  141. u32 BURST : 1;
  142. u32 SDL0 : 14;
  143. u32 LS0 : 1;
  144. u32 DDONE : 1;
  145. };
  146. struct pdma_txd_info3 {
  147. u32 SDP1;
  148. };
  149. struct pdma_txd_info4 {
  150. u32 VPRI_VIDX : 8;
  151. u32 SIDX : 4;
  152. u32 INSP : 1;
  153. u32 RESV : 2;
  154. u32 UDF : 5;
  155. u32 FP_BMAP : 8;
  156. u32 TSO : 1;
  157. u32 TUI_CO : 3;
  158. };
  159. struct pdma_tx_desc {
  160. struct pdma_txd_info1 txd_info1;
  161. struct pdma_txd_info2 txd_info2;
  162. struct pdma_txd_info3 txd_info3;
  163. struct pdma_txd_info4 txd_info4;
  164. };
  165. struct pdma_rxd_info1 {
  166. u32 PDP0;
  167. };
  168. struct pdma_rxd_info2 {
  169. u32 PLEN1 : 14;
  170. u32 LS1 : 1;
  171. u32 UN_USED : 1;
  172. u32 PLEN0 : 14;
  173. u32 LS0 : 1;
  174. u32 DDONE : 1;
  175. };
  176. struct pdma_rxd_info3 {
  177. u32 PDP1;
  178. };
  179. struct pdma_rxd_info4 {
  180. u32 FOE_ENTRY : 14;
  181. u32 CRSN : 5;
  182. u32 SP : 3;
  183. u32 L4F : 1;
  184. u32 L4VLD : 1;
  185. u32 TACK : 1;
  186. u32 IP4F : 1;
  187. u32 IP4 : 1;
  188. u32 IP6 : 1;
  189. u32 UN_USED : 4;
  190. };
  191. struct pdma_rx_desc {
  192. struct pdma_rxd_info1 rxd_info1;
  193. struct pdma_rxd_info2 rxd_info2;
  194. struct pdma_rxd_info3 rxd_info3;
  195. struct pdma_rxd_info4 rxd_info4;
  196. };
  197. struct mt7620_gsw_port_cfg {
  198. phy_interface_t mode;
  199. bool force_mode;
  200. bool duplex;
  201. u32 speed;
  202. int phy_addr;
  203. };
  204. struct mt7620_eth_priv {
  205. struct udevice *dev;
  206. void __iomem *fe_base;
  207. void __iomem *gsw_base;
  208. struct mii_dev *mdio_bus;
  209. struct pdma_tx_desc *tx_ring_noc;
  210. struct pdma_rx_desc *rx_ring_noc;
  211. int rx_dma_owner_idx0;
  212. int tx_cpu_owner_idx0;
  213. void *pkt_buf;
  214. void *tx_ring;
  215. void *rx_ring;
  216. struct reset_ctl_bulk rsts;
  217. struct clk_bulk clks;
  218. struct udevice *sysc;
  219. u32 ephy_num;
  220. bool port5_mt7530;
  221. struct gpio_desc gpio_swrst;
  222. struct mt7620_gsw_port_cfg port_cfg[3];
  223. };
  224. #define PDMA_TIMEOUT 100000
  225. #define NUM_TX_DESC 64
  226. #define NUM_RX_DESC 128
  227. #define NUM_FE_PHYS 5
  228. #define NUM_PORTS 7
  229. #define CPU_PORT_NUM 6
  230. #define NUM_MT7530_PHYS 5
  231. static void pdma_write(struct mt7620_eth_priv *priv, u32 reg, u32 val)
  232. {
  233. writel(val, priv->fe_base + PDMA_BASE + reg);
  234. }
  235. static void gdma_write(struct mt7620_eth_priv *priv, u32 reg, u32 val)
  236. {
  237. writel(val, priv->fe_base + GDMA_BASE + reg);
  238. }
  239. static void gdma_rmw(struct mt7620_eth_priv *priv, u32 reg, u32 clr, u32 set)
  240. {
  241. clrsetbits_le32(priv->fe_base + GDMA_BASE + reg, clr, set);
  242. }
  243. static u32 gsw_read(struct mt7620_eth_priv *priv, u32 reg)
  244. {
  245. return readl(priv->gsw_base + reg);
  246. }
  247. static void gsw_write(struct mt7620_eth_priv *priv, u32 reg, u32 val)
  248. {
  249. writel(val, priv->gsw_base + reg);
  250. }
  251. static void gsw_rmw(struct mt7620_eth_priv *priv, u32 reg, u32 clr, u32 set)
  252. {
  253. clrsetbits_le32(priv->gsw_base + reg, clr, set);
  254. }
  255. static int mt7620_mdio_rw(struct mt7620_eth_priv *priv, u32 phy, u32 reg,
  256. u32 data, u32 cmd)
  257. {
  258. int ret;
  259. u32 val;
  260. val = FIELD_PREP(MDIO_ST, 1) | FIELD_PREP(MDIO_CMD, cmd) |
  261. FIELD_PREP(MDIO_PHY_ADDR, phy) |
  262. FIELD_PREP(MDIO_REG_ADDR, reg);
  263. if (cmd == MDIO_CMD_WRITE)
  264. val |= FIELD_PREP(MDIO_RW_DATA, data);
  265. gsw_write(priv, GSW_PIAC, val);
  266. gsw_write(priv, GSW_PIAC, val | PHY_ACS_ST);
  267. ret = readl_poll_timeout(priv->gsw_base + GSW_PIAC, val,
  268. !(val & PHY_ACS_ST), 10000);
  269. if (ret) {
  270. dev_err(priv->dev, "mt7620_eth: MDIO access timeout\n");
  271. return ret;
  272. }
  273. if (cmd == MDIO_CMD_READ) {
  274. val = gsw_read(priv, GSW_PIAC);
  275. return FIELD_GET(MDIO_RW_DATA, val);
  276. }
  277. return 0;
  278. }
  279. static int mt7620_mii_read(struct mt7620_eth_priv *priv, u32 phy, u32 reg)
  280. {
  281. return mt7620_mdio_rw(priv, phy, reg, 0, MDIO_CMD_READ);
  282. }
  283. static int mt7620_mii_write(struct mt7620_eth_priv *priv, u32 phy, u32 reg,
  284. u16 val)
  285. {
  286. return mt7620_mdio_rw(priv, phy, reg, val, MDIO_CMD_WRITE);
  287. }
  288. static int mt7620_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  289. {
  290. struct mt7620_eth_priv *priv = bus->priv;
  291. int ret;
  292. if (devad < 0)
  293. return mt7620_mdio_rw(priv, addr, reg, 0, MDIO_CMD_READ);
  294. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG,
  295. FIELD_PREP(MMD_OP_MODE, MMD_ADDR) |
  296. FIELD_PREP(MMD_DEVAD, devad), MDIO_CMD_WRITE);
  297. if (ret)
  298. return ret;
  299. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, reg,
  300. MDIO_CMD_WRITE);
  301. if (ret)
  302. return ret;
  303. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG,
  304. FIELD_PREP(MMD_OP_MODE, MMD_DATA) |
  305. FIELD_PREP(MMD_DEVAD, devad), MDIO_CMD_WRITE);
  306. if (ret)
  307. return ret;
  308. return mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, 0,
  309. MDIO_CMD_READ);
  310. }
  311. static int mt7620_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  312. u16 val)
  313. {
  314. struct mt7620_eth_priv *priv = bus->priv;
  315. int ret;
  316. if (devad < 0)
  317. return mt7620_mdio_rw(priv, addr, reg, val, MDIO_CMD_WRITE);
  318. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG,
  319. FIELD_PREP(MMD_OP_MODE, MMD_ADDR) |
  320. FIELD_PREP(MMD_DEVAD, devad), MDIO_CMD_WRITE);
  321. if (ret)
  322. return ret;
  323. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, reg,
  324. MDIO_CMD_WRITE);
  325. if (ret)
  326. return ret;
  327. ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG,
  328. FIELD_PREP(MMD_OP_MODE, MMD_DATA) |
  329. FIELD_PREP(MMD_DEVAD, devad), MDIO_CMD_WRITE);
  330. if (ret)
  331. return ret;
  332. return mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, val,
  333. MDIO_CMD_WRITE);
  334. }
  335. static int mt7620_mdio_register(struct udevice *dev)
  336. {
  337. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  338. struct mii_dev *mdio_bus = mdio_alloc();
  339. int ret;
  340. if (!mdio_bus)
  341. return -ENOMEM;
  342. mdio_bus->read = mt7620_mdio_read;
  343. mdio_bus->write = mt7620_mdio_write;
  344. snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
  345. mdio_bus->priv = (void *)priv;
  346. ret = mdio_register(mdio_bus);
  347. if (ret)
  348. return ret;
  349. priv->mdio_bus = mdio_bus;
  350. return 0;
  351. }
  352. static int mt7530_reg_read(struct mt7620_eth_priv *priv, u32 reg, u32 *data)
  353. {
  354. int ret, low_word, high_word;
  355. /* Write page address */
  356. ret = mt7620_mii_write(priv, 0x1f, 0x1f,
  357. FIELD_GET(MT7530_REG_PAGE_ADDR, reg));
  358. if (ret)
  359. return ret;
  360. /* Read low word */
  361. low_word = mt7620_mii_read(priv, 0x1f, FIELD_GET(MT7530_REG_ADDR, reg));
  362. if (low_word < 0)
  363. return low_word;
  364. /* Read high word */
  365. high_word = mt7620_mii_read(priv, 0x1f, 0x10);
  366. if (high_word < 0)
  367. return high_word;
  368. if (data)
  369. *data = ((u32)high_word << 16) | ((u32)low_word & 0xffff);
  370. return 0;
  371. }
  372. static int mt7530_reg_write(struct mt7620_eth_priv *priv, u32 reg, u32 data)
  373. {
  374. int ret;
  375. /* Write page address */
  376. ret = mt7620_mii_write(priv, 0x1f, 0x1f,
  377. FIELD_GET(MT7530_REG_PAGE_ADDR, reg));
  378. if (ret)
  379. return ret;
  380. /* Write low word */
  381. ret = mt7620_mii_write(priv, 0x1f, FIELD_GET(MT7530_REG_ADDR, reg),
  382. data & 0xffff);
  383. if (ret)
  384. return ret;
  385. /* Write high word */
  386. return mt7620_mii_write(priv, 0x1f, 0x10, data >> 16);
  387. }
  388. static void mt7620_phy_restart_an(struct mt7620_eth_priv *priv, u32 phy)
  389. {
  390. u16 val;
  391. val = mt7620_mii_read(priv, phy, MII_BMCR);
  392. val |= BMCR_ANRESTART;
  393. mt7620_mii_write(priv, phy, MII_BMCR, val);
  394. }
  395. static void mt7620_gsw_ephy_init(struct mt7620_eth_priv *priv)
  396. {
  397. struct mt7620_sysc_chip_rev chip_rev;
  398. int ret;
  399. u32 i;
  400. ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CHIP_REV, &chip_rev);
  401. if (ret) {
  402. /* Assume MT7620A if misc_ioctl() failed */
  403. dev_warn(priv->dev, "mt7620_eth: failed to get chip rev\n");
  404. chip_rev.bga = 1;
  405. }
  406. /* global, page 4 */
  407. mt7620_mii_write(priv, 1, 31, 0x4000);
  408. mt7620_mii_write(priv, 1, 17, 0x7444);
  409. if (chip_rev.bga)
  410. mt7620_mii_write(priv, 1, 19, 0x0114);
  411. else
  412. mt7620_mii_write(priv, 1, 19, 0x0117);
  413. mt7620_mii_write(priv, 1, 22, 0x10cf);
  414. mt7620_mii_write(priv, 1, 25, 0x6212);
  415. mt7620_mii_write(priv, 1, 26, 0x0777);
  416. mt7620_mii_write(priv, 1, 29, 0x4000);
  417. mt7620_mii_write(priv, 1, 28, 0xc077);
  418. mt7620_mii_write(priv, 1, 24, 0x0000);
  419. /* global, page 3 */
  420. mt7620_mii_write(priv, 1, 31, 0x3000);
  421. mt7620_mii_write(priv, 1, 17, 0x4838);
  422. /* global, page 2 */
  423. mt7620_mii_write(priv, 1, 31, 0x2000);
  424. if (chip_rev.bga) {
  425. mt7620_mii_write(priv, 1, 21, 0x0515);
  426. mt7620_mii_write(priv, 1, 22, 0x0053);
  427. mt7620_mii_write(priv, 1, 23, 0x00bf);
  428. mt7620_mii_write(priv, 1, 24, 0x0aaf);
  429. mt7620_mii_write(priv, 1, 25, 0x0fad);
  430. mt7620_mii_write(priv, 1, 26, 0x0fc1);
  431. } else {
  432. mt7620_mii_write(priv, 1, 21, 0x0517);
  433. mt7620_mii_write(priv, 1, 22, 0x0fd2);
  434. mt7620_mii_write(priv, 1, 23, 0x00bf);
  435. mt7620_mii_write(priv, 1, 24, 0x0aab);
  436. mt7620_mii_write(priv, 1, 25, 0x00ae);
  437. mt7620_mii_write(priv, 1, 26, 0x0fff);
  438. }
  439. /* global, page 1 */
  440. mt7620_mii_write(priv, 1, 31, 0x1000);
  441. mt7620_mii_write(priv, 1, 17, 0xe7f8);
  442. /* local, page 0 */
  443. mt7620_mii_write(priv, 1, 31, 0x8000);
  444. for (i = 0; i < priv->ephy_num; i++)
  445. mt7620_mii_write(priv, i, 30, 0xa000);
  446. for (i = 0; i < priv->ephy_num; i++)
  447. mt7620_mii_write(priv, i, 4, 0x05e1);
  448. /* local, page 2 */
  449. mt7620_mii_write(priv, 1, 31, 0xa000);
  450. mt7620_mii_write(priv, 0, 16, 0x1111);
  451. mt7620_mii_write(priv, 1, 16, 0x1010);
  452. mt7620_mii_write(priv, 2, 16, 0x1515);
  453. mt7620_mii_write(priv, 3, 16, 0x0f0f);
  454. if (priv->ephy_num == NUM_FE_PHYS)
  455. mt7620_mii_write(priv, 4, 16, 0x1313);
  456. /* Restart auto-negotiation */
  457. for (i = 0; i < priv->ephy_num; i++)
  458. mt7620_phy_restart_an(priv, i);
  459. if (priv->port_cfg[0].phy_addr > 0)
  460. mt7620_phy_restart_an(priv, priv->port_cfg[0].phy_addr);
  461. if (priv->port_cfg[1].phy_addr > 0)
  462. mt7620_phy_restart_an(priv, priv->port_cfg[1].phy_addr);
  463. }
  464. static int mt7620_setup_gmac_mode(struct mt7620_eth_priv *priv, u32 gmac,
  465. phy_interface_t mode)
  466. {
  467. enum mt7620_sysc_ge_mode ge_mode;
  468. unsigned long req;
  469. int ret;
  470. switch (gmac) {
  471. case 1:
  472. req = MT7620_SYSC_IOCTL_SET_GE1_MODE;
  473. break;
  474. case 2:
  475. req = MT7620_SYSC_IOCTL_SET_GE2_MODE;
  476. break;
  477. default:
  478. /* Should not reach here */
  479. return -EINVAL;
  480. }
  481. switch (mode) {
  482. case PHY_INTERFACE_MODE_MII:
  483. ge_mode = MT7620_SYSC_GE_MII;
  484. break;
  485. case PHY_INTERFACE_MODE_RMII:
  486. ge_mode = MT7620_SYSC_GE_RMII;
  487. break;
  488. case PHY_INTERFACE_MODE_RGMII:
  489. ge_mode = MT7620_SYSC_GE_RGMII;
  490. break;
  491. case PHY_INTERFACE_MODE_NONE:
  492. if (gmac == 2)
  493. ge_mode = MT7620_SYSC_GE_ESW_PHY;
  494. else
  495. ge_mode = MT7620_SYSC_GE_RGMII;
  496. break;
  497. default:
  498. /* Should not reach here */
  499. return -EINVAL;
  500. }
  501. ret = misc_ioctl(priv->sysc, req, &ge_mode);
  502. if (ret)
  503. dev_warn(priv->dev, "mt7620_eth: failed to set GE%u mode\n",
  504. gmac);
  505. return 0;
  506. }
  507. static void mt7620_gsw_setup_port(struct mt7620_eth_priv *priv, u32 port,
  508. struct mt7620_gsw_port_cfg *port_cfg)
  509. {
  510. u32 pmcr;
  511. if (port_cfg->mode == PHY_INTERFACE_MODE_NONE) {
  512. if (port == 5) {
  513. gsw_write(priv, GSW_PMCR(port), FORCE_MODE);
  514. return;
  515. }
  516. port_cfg->force_mode = port == CPU_PORT_NUM ? true : false;
  517. }
  518. pmcr = FIELD_PREP(IPG_CFG, IPG_96BIT_WITH_SHORT_IPG) | MAC_MODE |
  519. MAC_TX_EN | MAC_RX_EN | BKOFF_EN | BACKPR_EN;
  520. if (port_cfg->force_mode) {
  521. pmcr |= FORCE_MODE | FORCE_RX_FC | FORCE_TX_FC |
  522. FIELD_PREP(FORCE_SPEED, port_cfg->speed) | FORCE_LINK;
  523. if (port_cfg->duplex)
  524. pmcr |= FORCE_DUPLEX;
  525. }
  526. gsw_write(priv, GSW_PMCR(port), pmcr);
  527. }
  528. static void mt7620_gsw_set_port_isolation(struct mt7620_eth_priv *priv)
  529. {
  530. u32 i;
  531. for (i = 0; i < NUM_PORTS; i++) {
  532. /* Set port matrix mode */
  533. if (i != CPU_PORT_NUM)
  534. gsw_write(priv, GSW_PCR(i),
  535. FIELD_PREP(PORT_MATRIX, 0x40));
  536. else
  537. gsw_write(priv, GSW_PCR(i),
  538. FIELD_PREP(PORT_MATRIX, 0x3f));
  539. /* Set port mode to user port */
  540. gsw_write(priv, GSW_PVC(i), FIELD_PREP(STAG_VPID, 0x8100) |
  541. FIELD_PREP(VLAN_ATTR, VLAN_ATTR_USER));
  542. }
  543. }
  544. static void mt7620_gsw_setup_phy_polling(struct mt7620_eth_priv *priv)
  545. {
  546. int phy_addr_st, phy_addr_end;
  547. if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NONE)
  548. priv->ephy_num = NUM_FE_PHYS;
  549. else
  550. priv->ephy_num = NUM_FE_PHYS - 1;
  551. if (priv->port_cfg[0].phy_addr < 0 && priv->port_cfg[1].phy_addr < 0)
  552. return;
  553. if (priv->port_cfg[0].phy_addr > 0 && priv->port_cfg[1].phy_addr > 0) {
  554. phy_addr_st = priv->port_cfg[0].phy_addr;
  555. phy_addr_end = priv->port_cfg[1].phy_addr;
  556. } else if (priv->port_cfg[0].phy_addr > 0) {
  557. phy_addr_st = priv->port_cfg[0].phy_addr;
  558. phy_addr_end = priv->port_cfg[0].phy_addr + 1;
  559. } else {
  560. phy_addr_st = 4;
  561. phy_addr_end = priv->port_cfg[1].phy_addr;
  562. }
  563. gsw_rmw(priv, GSW_PPSC, PHY_AP_END_ADDR | PHY_AP_START_ADDR,
  564. PHY_AP_EN | FIELD_PREP(PHY_AP_START_ADDR, phy_addr_st) |
  565. FIELD_PREP(PHY_AP_END_ADDR, phy_addr_end));
  566. }
  567. static void mt7530_gsw_set_port_isolation(struct mt7620_eth_priv *priv)
  568. {
  569. u32 i;
  570. for (i = 0; i < NUM_PORTS; i++) {
  571. /* Set port matrix mode */
  572. if (i != CPU_PORT_NUM)
  573. mt7530_reg_write(priv, GSW_PCR(i),
  574. FIELD_PREP(PORT_MATRIX, 0x40));
  575. else
  576. mt7530_reg_write(priv, GSW_PCR(i),
  577. FIELD_PREP(PORT_MATRIX, 0x3f));
  578. /* Set port mode to user port */
  579. mt7530_reg_write(priv, GSW_PVC(i),
  580. FIELD_PREP(STAG_VPID, 0x8100) |
  581. FIELD_PREP(VLAN_ATTR, VLAN_ATTR_USER));
  582. }
  583. }
  584. static void mt7620_gsw_config_mt7530(struct mt7620_eth_priv *priv)
  585. {
  586. u16 phy_val;
  587. u32 i, val;
  588. /* Disable internal PHY, set PHY base to 12 */
  589. gsw_write(priv, GSW_GPC1, PHY_DIS | FIELD_PREP(PHY_BASE, 12) |
  590. TX_CLK_MODE | RX_CLK_MODE);
  591. /* MT7530 reset deassert */
  592. dm_gpio_set_value(&priv->gpio_swrst, 1);
  593. mdelay(1000);
  594. /* Turn off PHYs */
  595. for (i = 0; i < NUM_MT7530_PHYS; i++) {
  596. phy_val = mt7620_mii_read(priv, i, MII_BMCR);
  597. phy_val |= BMCR_PDOWN;
  598. mt7620_mii_write(priv, i, MII_BMCR, phy_val);
  599. }
  600. /* Force MAC link down before reset */
  601. mt7530_reg_write(priv, GSW_PMCR(5), FORCE_MODE);
  602. mt7530_reg_write(priv, GSW_PMCR(6), FORCE_MODE);
  603. /* MT7530 soft reset */
  604. mt7530_reg_write(priv, MT7530_SYS_CTRL, SW_SYS_RST | SW_REG_RST);
  605. udelay(100);
  606. /* MT7530 port6 force to 1G (connects to MT7620 GSW port5) */
  607. mt7530_reg_write(priv, GSW_PMCR(6),
  608. FIELD_PREP(IPG_CFG, IPG_96BIT_WITH_SHORT_IPG) |
  609. MAC_MODE | FORCE_MODE | MAC_TX_EN | MAC_RX_EN |
  610. BKOFF_EN | BACKPR_EN | FORCE_RX_FC | FORCE_TX_FC |
  611. FIELD_PREP(FORCE_SPEED, FORCE_SPEED_1000) |
  612. FORCE_DUPLEX | FORCE_LINK);
  613. /* Disable MT7530 port5 */
  614. mt7530_reg_read(priv, MT7530_MHWTRAP, &val);
  615. val |= P5_INTF_SEL_GMAC5 | P5_INTF_DIS;
  616. mt7530_reg_write(priv, MT7530_MHWTRAP, val);
  617. /* Isolate each ports */
  618. mt7530_gsw_set_port_isolation(priv);
  619. /* Turn on PHYs */
  620. for (i = 0; i < NUM_MT7530_PHYS; i++) {
  621. phy_val = mt7620_mii_read(priv, i, MII_BMCR);
  622. phy_val &= ~BMCR_PDOWN;
  623. mt7620_mii_write(priv, i, MII_BMCR, phy_val);
  624. }
  625. /* Restart auto-negotiation */
  626. for (i = 0; i < NUM_MT7530_PHYS; i++)
  627. mt7620_phy_restart_an(priv, i);
  628. }
  629. static void mt7620_gsw_init(struct mt7620_eth_priv *priv)
  630. {
  631. /* If port5 connects to MT7530 Giga-switch, reset it first */
  632. if (priv->port5_mt7530)
  633. dm_gpio_set_value(&priv->gpio_swrst, 0);
  634. /* Set forward control */
  635. gsw_write(priv, GSW_MFC, FIELD_PREP(BC_FFP, 0x7f) |
  636. FIELD_PREP(UNM_FFP, 0x7f) | FIELD_PREP(UNU_FFP, 0x7f) |
  637. CPU_EN | FIELD_PREP(CPU_PORT, CPU_PORT_NUM));
  638. /* Set GMAC mode (GMAC1 -> Port5, GMAC2 -> Port4) */
  639. mt7620_setup_gmac_mode(priv, 1, priv->port_cfg[1].mode);
  640. mt7620_setup_gmac_mode(priv, 2, priv->port_cfg[0].mode);
  641. /* port_cfg[2] is CPU port */
  642. priv->port_cfg[2].force_mode = true;
  643. priv->port_cfg[2].duplex = true;
  644. priv->port_cfg[2].speed = FORCE_SPEED_1000;
  645. /* Configure GSW MAC port */
  646. mt7620_gsw_setup_port(priv, 4, &priv->port_cfg[0]);
  647. mt7620_gsw_setup_port(priv, 5, &priv->port_cfg[1]);
  648. mt7620_gsw_setup_port(priv, 6, &priv->port_cfg[2]);
  649. /* Isolate each port */
  650. mt7620_gsw_set_port_isolation(priv);
  651. /* Polling external phy if exists */
  652. mt7620_gsw_setup_phy_polling(priv);
  653. /* Configure ephy */
  654. mt7620_gsw_ephy_init(priv);
  655. /* If port5 connects to MT7530 Giga-switch, do initialization */
  656. if (priv->port5_mt7530)
  657. mt7620_gsw_config_mt7530(priv);
  658. }
  659. static void mt7620_eth_fifo_init(struct mt7620_eth_priv *priv)
  660. {
  661. uintptr_t pkt_base = (uintptr_t)priv->pkt_buf;
  662. int i;
  663. memset(priv->tx_ring, 0, NUM_TX_DESC * sizeof(struct pdma_tx_desc));
  664. memset(priv->rx_ring, 0, NUM_RX_DESC * sizeof(struct pdma_rx_desc));
  665. memset(priv->pkt_buf, 0, (NUM_TX_DESC + NUM_RX_DESC) * PKTSIZE_ALIGN);
  666. priv->tx_ring_noc = (void *)CKSEG1ADDR((uintptr_t)priv->tx_ring);
  667. priv->rx_ring_noc = (void *)CKSEG1ADDR((uintptr_t)priv->rx_ring);
  668. priv->rx_dma_owner_idx0 = 0;
  669. priv->tx_cpu_owner_idx0 = 0;
  670. for (i = 0; i < NUM_TX_DESC; i++) {
  671. priv->tx_ring_noc[i].txd_info2.LS0 = 1;
  672. priv->tx_ring_noc[i].txd_info2.DDONE = 1;
  673. priv->tx_ring_noc[i].txd_info4.FP_BMAP = GDMA_DST_PORT_CPU;
  674. priv->tx_ring_noc[i].txd_info1.SDP0 = CPHYSADDR(pkt_base);
  675. pkt_base += PKTSIZE_ALIGN;
  676. }
  677. for (i = 0; i < NUM_RX_DESC; i++) {
  678. priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
  679. priv->rx_ring_noc[i].rxd_info1.PDP0 = CPHYSADDR(pkt_base);
  680. pkt_base += PKTSIZE_ALIGN;
  681. }
  682. pdma_write(priv, TX_BASE_PTR0, CPHYSADDR(priv->tx_ring_noc));
  683. pdma_write(priv, TX_MAX_CNT0, NUM_TX_DESC);
  684. pdma_write(priv, TX_CTX_IDX0, priv->tx_cpu_owner_idx0);
  685. pdma_write(priv, RX_BASE_PTR0, CPHYSADDR(priv->rx_ring_noc));
  686. pdma_write(priv, RX_MAX_CNT0, NUM_RX_DESC);
  687. pdma_write(priv, RX_CALC_IDX0, NUM_RX_DESC - 1);
  688. pdma_write(priv, PDMA_RST_IDX, RST_DTX_IDX0 | RST_DRX_IDX0);
  689. }
  690. static int mt7620_eth_start(struct udevice *dev)
  691. {
  692. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  693. mt7620_eth_fifo_init(priv);
  694. gdma_rmw(priv, GDMA_FWD_CFG, GDMA_DST_PORT,
  695. FIELD_PREP(GDMA_DST_PORT, GDMA_DST_PORT_CPU));
  696. pdma_write(priv, PDMA_GLO_CFG,
  697. FIELD_PREP(PDMA_BT_SIZE, PDMA_BT_SIZE_32B) |
  698. TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
  699. udelay(500);
  700. return 0;
  701. }
  702. static void mt7620_eth_stop(struct udevice *dev)
  703. {
  704. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  705. u32 val;
  706. int ret;
  707. pdma_write(priv, PDMA_GLO_CFG,
  708. FIELD_PREP(PDMA_BT_SIZE, PDMA_BT_SIZE_32B));
  709. udelay(500);
  710. ret = readl_poll_timeout(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG,
  711. val, !(val & (RX_DMA_BUSY | TX_DMA_BUSY)),
  712. PDMA_TIMEOUT);
  713. if (ret)
  714. dev_warn(dev, "mt7620_eth: PDMA is still busy\n");
  715. }
  716. static int mt7620_eth_write_hwaddr(struct udevice *dev)
  717. {
  718. struct eth_pdata *pdata = dev_get_plat(dev);
  719. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  720. unsigned char *mac = pdata->enetaddr;
  721. u32 macaddr_lsb, macaddr_msb;
  722. macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
  723. macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
  724. ((u32)mac[4] << 8) | (u32)mac[5];
  725. gdma_write(priv, GDMA_MAC_ADRH, macaddr_msb);
  726. gdma_write(priv, GDMA_MAC_ADRL, macaddr_lsb);
  727. return 0;
  728. }
  729. static int mt7620_eth_send(struct udevice *dev, void *packet, int length)
  730. {
  731. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  732. u32 idx = priv->tx_cpu_owner_idx0;
  733. void *pkt_base;
  734. if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
  735. printf("mt7620_eth: TX DMA descriptor ring is full\n");
  736. return -EPERM;
  737. }
  738. pkt_base = (void *)CKSEG0ADDR(priv->tx_ring_noc[idx].txd_info1.SDP0);
  739. memcpy(pkt_base, packet, length);
  740. flush_dcache_range((ulong)pkt_base, (ulong)pkt_base + length);
  741. priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
  742. priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
  743. priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
  744. pdma_write(priv, TX_CTX_IDX0, priv->tx_cpu_owner_idx0);
  745. return 0;
  746. }
  747. static int mt7620_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  748. {
  749. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  750. u32 idx = priv->rx_dma_owner_idx0, length;
  751. uchar *pkt_base;
  752. if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
  753. debug("mt7620_eth: RX DMA descriptor ring is empty\n");
  754. return -EAGAIN;
  755. }
  756. length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
  757. pkt_base = (void *)CKSEG0ADDR(priv->rx_ring_noc[idx].rxd_info1.PDP0);
  758. invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base + length);
  759. if (packetp)
  760. *packetp = pkt_base;
  761. return length;
  762. }
  763. static int mt7620_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  764. {
  765. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  766. u32 idx = priv->rx_dma_owner_idx0;
  767. priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
  768. priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
  769. priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
  770. pdma_write(priv, RX_CALC_IDX0, idx);
  771. priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
  772. return 0;
  773. }
  774. static const struct eth_ops mt7620_eth_ops = {
  775. .start = mt7620_eth_start,
  776. .stop = mt7620_eth_stop,
  777. .send = mt7620_eth_send,
  778. .recv = mt7620_eth_recv,
  779. .free_pkt = mt7620_eth_free_pkt,
  780. .write_hwaddr = mt7620_eth_write_hwaddr,
  781. };
  782. static int mt7620_eth_alloc_rings_pkts(struct mt7620_eth_priv *priv)
  783. {
  784. priv->tx_ring = memalign(ARCH_DMA_MINALIGN,
  785. NUM_TX_DESC * sizeof(struct pdma_tx_desc));
  786. if (!priv->tx_ring) {
  787. dev_err(priv->dev, "mt7620_eth: unable to alloc tx ring\n");
  788. return -ENOMEM;
  789. }
  790. priv->rx_ring = memalign(ARCH_DMA_MINALIGN,
  791. NUM_RX_DESC * sizeof(struct pdma_rx_desc));
  792. if (!priv->rx_ring) {
  793. dev_err(priv->dev, "mt7620_eth: unable to alloc rx ring\n");
  794. goto cleanup;
  795. }
  796. priv->pkt_buf = memalign(ARCH_DMA_MINALIGN,
  797. (NUM_TX_DESC + NUM_RX_DESC) * PKTSIZE_ALIGN);
  798. if (!priv->pkt_buf) {
  799. dev_err(priv->dev, "mt7620_eth: unable to alloc pkt buffer\n");
  800. goto cleanup;
  801. }
  802. return 0;
  803. cleanup:
  804. if (priv->tx_ring)
  805. free(priv->tx_ring);
  806. if (priv->rx_ring)
  807. free(priv->rx_ring);
  808. return -ENOMEM;
  809. }
  810. static void mt7620_eth_free_rings_pkts(struct mt7620_eth_priv *priv)
  811. {
  812. free(priv->tx_ring);
  813. free(priv->rx_ring);
  814. free(priv->pkt_buf);
  815. }
  816. static int mt7620_eth_probe(struct udevice *dev)
  817. {
  818. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  819. u32 pcie_mode = MT7620_SYSC_PCIE_RC_MODE;
  820. int ret;
  821. misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_SET_PCIE_MODE, &pcie_mode);
  822. clk_enable_bulk(&priv->clks);
  823. reset_assert_bulk(&priv->rsts);
  824. udelay(100);
  825. reset_deassert_bulk(&priv->rsts);
  826. udelay(1000);
  827. ret = mt7620_eth_alloc_rings_pkts(priv);
  828. if (ret)
  829. return ret;
  830. ret = mt7620_mdio_register(dev);
  831. if (ret)
  832. dev_warn(dev, "mt7620_eth: failed to register MDIO bus\n");
  833. mt7620_gsw_init(priv);
  834. return 0;
  835. }
  836. static int mt7620_eth_remove(struct udevice *dev)
  837. {
  838. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  839. mt7620_eth_stop(dev);
  840. mt7620_eth_free_rings_pkts(priv);
  841. return 0;
  842. }
  843. static int mt7620_eth_parse_gsw_port(struct mt7620_eth_priv *priv, u32 idx,
  844. ofnode node)
  845. {
  846. ofnode subnode;
  847. const char *str;
  848. int mode, speed, ret;
  849. u32 phy_addr;
  850. str = ofnode_read_string(node, "phy-mode");
  851. if (str) {
  852. mode = phy_get_interface_by_name(str);
  853. if (mode < 0) {
  854. dev_err(priv->dev, "mt7620_eth: invalid phy-mode\n");
  855. return -EINVAL;
  856. }
  857. switch (mode) {
  858. case PHY_INTERFACE_MODE_MII:
  859. case PHY_INTERFACE_MODE_RMII:
  860. case PHY_INTERFACE_MODE_RGMII:
  861. case PHY_INTERFACE_MODE_NONE:
  862. break;
  863. default:
  864. dev_err(priv->dev,
  865. "mt7620_eth: unsupported phy-mode\n");
  866. return -ENOTSUPP;
  867. }
  868. priv->port_cfg[idx].mode = mode;
  869. } else {
  870. priv->port_cfg[idx].mode = PHY_INTERFACE_MODE_NONE;
  871. }
  872. subnode = ofnode_find_subnode(node, "fixed-link");
  873. if (ofnode_valid(subnode)) {
  874. priv->port_cfg[idx].force_mode = 1;
  875. priv->port_cfg[idx].duplex = ofnode_read_bool(subnode,
  876. "full-duplex");
  877. speed = ofnode_read_u32_default(subnode, "speed", 0);
  878. switch (speed) {
  879. case SPEED_10:
  880. priv->port_cfg[idx].speed = FORCE_SPEED_10;
  881. break;
  882. case SPEED_100:
  883. priv->port_cfg[idx].speed = FORCE_SPEED_100;
  884. break;
  885. case SPEED_1000:
  886. priv->port_cfg[idx].speed = FORCE_SPEED_1000;
  887. break;
  888. default:
  889. dev_err(priv->dev,
  890. "mt7620_eth: invalid speed for fixed-link\n");
  891. return -EINVAL;
  892. }
  893. if (idx == 1 && ofnode_read_bool(subnode, "mediatek,mt7530")) {
  894. priv->port5_mt7530 = true;
  895. ret = gpio_request_by_name_nodev(subnode,
  896. "mediatek,mt7530-reset", 0, &priv->gpio_swrst,
  897. GPIOD_IS_OUT);
  898. if (ret) {
  899. dev_err(priv->dev,
  900. "mt7620_eth: missing mt7530 reset gpio\n");
  901. return ret;
  902. }
  903. }
  904. }
  905. ret = ofnode_read_u32(node, "phy-addr", &phy_addr);
  906. if (!ret) {
  907. if (phy_addr > 31 || (idx == 0 && phy_addr < 3) ||
  908. (idx == 1 && phy_addr < 4)) {
  909. dev_err(priv->dev, "mt7620_eth: invalid phy address\n");
  910. return -EINVAL;
  911. }
  912. priv->port_cfg[idx].phy_addr = phy_addr;
  913. } else {
  914. priv->port_cfg[idx].phy_addr = -1;
  915. }
  916. return 0;
  917. }
  918. static int mt7620_eth_parse_gsw_cfg(struct udevice *dev)
  919. {
  920. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  921. ofnode subnode;
  922. int ret;
  923. subnode = ofnode_find_subnode(dev_ofnode(dev), "port4");
  924. if (ofnode_valid(subnode)) {
  925. ret = mt7620_eth_parse_gsw_port(priv, 0, subnode);
  926. if (ret)
  927. return ret;
  928. } else {
  929. priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NONE;
  930. }
  931. subnode = ofnode_find_subnode(dev_ofnode(dev), "port5");
  932. if (ofnode_valid(subnode))
  933. return mt7620_eth_parse_gsw_port(priv, 1, subnode);
  934. priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NONE;
  935. return 0;
  936. }
  937. static int mt7620_eth_of_to_plat(struct udevice *dev)
  938. {
  939. struct eth_pdata *pdata = dev_get_plat(dev);
  940. struct mt7620_eth_priv *priv = dev_get_priv(dev);
  941. struct ofnode_phandle_args sysc_args;
  942. int ret;
  943. pdata->iobase = dev_read_addr(dev);
  944. priv->dev = dev;
  945. ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "mediatek,sysc", NULL,
  946. 0, 0, &sysc_args);
  947. if (ret) {
  948. dev_err(dev, "mt7620_eth: sysc property not found\n");
  949. return ret;
  950. }
  951. ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
  952. &priv->sysc);
  953. if (ret) {
  954. dev_err(dev, "mt7620_eth: failed to sysc device\n");
  955. return ret;
  956. }
  957. priv->fe_base = dev_remap_addr_name(dev, "fe");
  958. if (!priv->fe_base) {
  959. dev_err(dev, "mt7620_eth: failed to map fe registers\n");
  960. return -EINVAL;
  961. }
  962. priv->gsw_base = dev_remap_addr_name(dev, "esw");
  963. if (!priv->gsw_base) {
  964. dev_err(dev, "mt7620_eth: failed to map esw registers\n");
  965. return -EINVAL;
  966. }
  967. ret = reset_get_bulk(dev, &priv->rsts);
  968. if (ret) {
  969. dev_err(dev, "mt7620_eth: failed to get resetctl\n");
  970. return ret;
  971. }
  972. ret = clk_get_bulk(dev, &priv->clks);
  973. if (ret) {
  974. dev_err(dev, "mt7620_eth: failed to get clocks\n");
  975. return ret;
  976. }
  977. return mt7620_eth_parse_gsw_cfg(dev);
  978. }
  979. static const struct udevice_id mt7620_eth_ids[] = {
  980. { .compatible = "mediatek,mt7620-eth" },
  981. {}
  982. };
  983. U_BOOT_DRIVER(mt7620_eth) = {
  984. .name = "mt7620-eth",
  985. .id = UCLASS_ETH,
  986. .of_match = mt7620_eth_ids,
  987. .of_to_plat = mt7620_eth_of_to_plat,
  988. .plat_auto = sizeof(struct eth_pdata),
  989. .probe = mt7620_eth_probe,
  990. .remove = mt7620_eth_remove,
  991. .ops = &mt7620_eth_ops,
  992. .priv_auto = sizeof(struct mt7620_eth_priv),
  993. };