dnet.h 4.9 KB

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  1. /*
  2. * Dave Ethernet Controller driver
  3. *
  4. * Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef __DRIVERS_DNET_H__
  11. #define __DRIVERS_DNET_H__
  12. #define DRIVERNAME "dnet"
  13. struct dnet_registers {
  14. /* ALL DNET FIFO REGISTERS */
  15. u32 RX_LEN_FIFO;
  16. u32 RX_DATA_FIFO;
  17. u32 TX_LEN_FIFO;
  18. u32 TX_DATA_FIFO;
  19. u32 pad1[0x3c];
  20. /* ALL DNET CONTROL/STATUS REGISTERS */
  21. u32 VERCAPS;
  22. u32 INTR_SRC;
  23. u32 INTR_ENB;
  24. u32 RX_STATUS;
  25. u32 TX_STATUS;
  26. u32 RX_FRAMES_CNT;
  27. u32 TX_FRAMES_CNT;
  28. u32 RX_FIFO_TH;
  29. u32 TX_FIFO_TH;
  30. u32 SYS_CTL;
  31. u32 PAUSE_TMR;
  32. u32 RX_FIFO_WCNT;
  33. u32 TX_FIFO_WCNT;
  34. u32 pad2[0x33];
  35. /* ALL DNET MAC REGISTERS */
  36. u32 MACREG_DATA; /* Mac-Reg Data */
  37. u32 MACREG_ADDR; /* Mac-Reg Addr */
  38. u32 pad3[0x3e];
  39. /* ALL DNET RX STATISTICS COUNTERS */
  40. u32 RX_PKT_IGNR_CNT;
  41. u32 RX_LEN_CHK_ERR_CNT;
  42. u32 RX_LNG_FRM_CNT;
  43. u32 RX_SHRT_FRM_CNT;
  44. u32 RX_IPG_VIOL_CNT;
  45. u32 RX_CRC_ERR_CNT;
  46. u32 RX_OK_PKT_CNT;
  47. u32 RX_CTL_FRM_CNT;
  48. u32 RX_PAUSE_FRM_CNT;
  49. u32 RX_MULTICAST_CNT;
  50. u32 RX_BROADCAST_CNT;
  51. u32 RX_VLAN_TAG_CNT;
  52. u32 RX_PRE_SHRINK_CNT;
  53. u32 RX_DRIB_NIB_CNT;
  54. u32 RX_UNSUP_OPCD_CNT;
  55. u32 RX_BYTE_CNT;
  56. u32 pad4[0x30];
  57. /* DNET TX STATISTICS COUNTERS */
  58. u32 TX_UNICAST_CNT;
  59. u32 TX_PAUSE_FRM_CNT;
  60. u32 TX_MULTICAST_CNT;
  61. u32 TX_BRDCAST_CNT;
  62. u32 TX_VLAN_TAG_CNT;
  63. u32 TX_BAD_FCS_CNT;
  64. u32 TX_JUMBO_CNT;
  65. u32 TX_BYTE_CNT;
  66. };
  67. /* SOME INTERNAL MAC-CORE REGISTER */
  68. #define DNET_INTERNAL_MODE_REG 0x0
  69. #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
  70. #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
  71. #define DNET_INTERNAL_IGP_REG 0x8
  72. #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
  73. #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
  74. #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
  75. #define DNET_INTERNAL_TX_RX_STS_REG 0x12
  76. #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
  77. #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
  78. #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
  79. #define DNET_INTERNAL_WRITE (1 << 31)
  80. /* MAC-CORE REGISTER FIELDS */
  81. /* MAC-CORE MODE REGISTER FIELDS */
  82. #define DNET_INTERNAL_MODE_GBITEN (1 << 0)
  83. #define DNET_INTERNAL_MODE_FCEN (1 << 1)
  84. #define DNET_INTERNAL_MODE_RXEN (1 << 2)
  85. #define DNET_INTERNAL_MODE_TXEN (1 << 3)
  86. /* MAC-CORE RXTX CONTROL REGISTER FIELDS */
  87. #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
  88. #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
  89. #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
  90. #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
  91. #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
  92. #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
  93. #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
  94. #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
  95. #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
  96. /* SYSTEM CONTROL REGISTER FIELDS */
  97. #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
  98. #define DNET_SYS_CTL_SENDPAUSE (1 << 2)
  99. #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
  100. #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
  101. /* TX STATUS REGISTER FIELDS */
  102. #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
  103. #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
  104. /* INTERRUPT SOURCE REGISTER FIELDS */
  105. #define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
  106. #define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
  107. #define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
  108. #define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
  109. #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
  110. #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
  111. #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
  112. #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
  113. #define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
  114. #define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
  115. #define DNET_INTR_SRC_PHY (1 << 19)
  116. /* INTERRUPT ENABLE REGISTER FIELDS */
  117. #define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
  118. #define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
  119. #define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
  120. #define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
  121. #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
  122. #define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
  123. #define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
  124. #define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
  125. #define DNET_INTR_ENB_RX_ERROR (1 << 11)
  126. #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
  127. #define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
  128. #define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
  129. #define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
  130. #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
  131. /*
  132. * Capabilities. Used by the driver to know the capabilities that
  133. * the ethernet controller inside the FPGA have.
  134. */
  135. #define DNET_HAS_MDIO (1 << 0)
  136. #define DNET_HAS_IRQ (1 << 1)
  137. #define DNET_HAS_GIGABIT (1 << 2)
  138. #define DNET_HAS_DMA (1 << 3)
  139. #define DNET_HAS_MII (1 << 4) /* or GMII */
  140. #define DNET_HAS_RMII (1 << 5) /* or RGMII */
  141. #define DNET_CAPS_MASK 0xFFFF
  142. #define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
  143. #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
  144. #define DNET_FIFO_TX_DATA_AE_TH (384)
  145. #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
  146. #endif