socfpga_arria10.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. */
  5. #include <image.h>
  6. #include <log.h>
  7. #include <asm/global_data.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fpga_manager.h>
  10. #include <asm/arch/reset_manager.h>
  11. #include <asm/arch/system_manager.h>
  12. #include <asm/arch/sdram.h>
  13. #include <asm/arch/misc.h>
  14. #include <altera.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <common.h>
  17. #include <dm.h>
  18. #include <dm/ofnode.h>
  19. #include <errno.h>
  20. #include <fs_loader.h>
  21. #include <wait_bit.h>
  22. #include <watchdog.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #define CFGWDTH_32 1
  26. #define MIN_BITSTREAM_SIZECHECK 230
  27. #define ENCRYPTION_OFFSET 69
  28. #define COMPRESSION_OFFSET 229
  29. #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
  30. #define FPGA_TIMEOUT_CNT 0x1000000
  31. #define DEFAULT_DDR_LOAD_ADDRESS 0x400
  32. DECLARE_GLOBAL_DATA_PTR;
  33. static const struct socfpga_fpga_manager *fpga_manager_base =
  34. (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  35. static void fpgamgr_set_cd_ratio(unsigned long ratio);
  36. static uint32_t fpgamgr_get_msel(void)
  37. {
  38. u32 reg;
  39. reg = readl(&fpga_manager_base->imgcfg_stat);
  40. reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
  41. ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
  42. return reg;
  43. }
  44. static void fpgamgr_set_cfgwdth(int width)
  45. {
  46. if (width)
  47. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  48. ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  49. else
  50. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  51. ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
  52. }
  53. int is_fpgamgr_user_mode(void)
  54. {
  55. return (readl(&fpga_manager_base->imgcfg_stat) &
  56. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
  57. }
  58. static int wait_for_user_mode(void)
  59. {
  60. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  61. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
  62. 1, FPGA_TIMEOUT_MSEC, false);
  63. }
  64. int is_fpgamgr_early_user_mode(void)
  65. {
  66. return (readl(&fpga_manager_base->imgcfg_stat) &
  67. ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
  68. }
  69. int fpgamgr_wait_early_user_mode(void)
  70. {
  71. u32 sync_data = 0xffffffff;
  72. u32 i = 0;
  73. unsigned start = get_timer(0);
  74. unsigned long cd_ratio;
  75. /* Getting existing CDRATIO */
  76. cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
  77. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
  78. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
  79. /* Using CDRATIO_X1 for better compatibility */
  80. fpgamgr_set_cd_ratio(CDRATIO_x1);
  81. while (!is_fpgamgr_early_user_mode()) {
  82. if (get_timer(start) > FPGA_TIMEOUT_MSEC)
  83. return -ETIMEDOUT;
  84. fpgamgr_program_write((const long unsigned int *)&sync_data,
  85. sizeof(sync_data));
  86. udelay(FPGA_TIMEOUT_MSEC);
  87. i++;
  88. }
  89. debug("FPGA: Additional %i sync word needed\n", i);
  90. /* restoring original CDRATIO */
  91. fpgamgr_set_cd_ratio(cd_ratio);
  92. return 0;
  93. }
  94. /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
  95. static int wait_for_nconfig_pin_and_nstatus_pin(void)
  96. {
  97. unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
  98. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
  99. /*
  100. * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
  101. * de-asserted, timeout at 1000ms
  102. */
  103. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
  104. true, FPGA_TIMEOUT_MSEC, false);
  105. }
  106. static int wait_for_f2s_nstatus_pin(unsigned long value)
  107. {
  108. /* Poll until f2s to specific value, timeout at 1000ms */
  109. return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
  110. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
  111. value, FPGA_TIMEOUT_MSEC, false);
  112. }
  113. /* set CD ratio */
  114. static void fpgamgr_set_cd_ratio(unsigned long ratio)
  115. {
  116. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  117. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  118. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  119. (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
  120. ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
  121. }
  122. /* get the MSEL value, verify we are set for FPP configuration mode */
  123. static int fpgamgr_verify_msel(void)
  124. {
  125. u32 msel = fpgamgr_get_msel();
  126. if (msel & ~BIT(0)) {
  127. printf("Fail: read msel=%d\n", msel);
  128. return -EPERM;
  129. }
  130. return 0;
  131. }
  132. /*
  133. * Write cdratio and cdwidth based on whether the bitstream is compressed
  134. * and/or encoded
  135. */
  136. static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
  137. size_t rbf_size)
  138. {
  139. unsigned int cd_ratio;
  140. bool encrypt, compress;
  141. /*
  142. * According to the bitstream specification,
  143. * both encryption and compression status are
  144. * in location before offset 230 of the buffer.
  145. */
  146. if (rbf_size < MIN_BITSTREAM_SIZECHECK)
  147. return -EINVAL;
  148. encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
  149. encrypt = encrypt != 0;
  150. compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
  151. compress = !compress;
  152. debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
  153. debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
  154. debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
  155. compress);
  156. /*
  157. * from the register map description of cdratio in imgcfg_ctrl_02:
  158. * Normal Configuration : 32bit Passive Parallel
  159. * Partial Reconfiguration : 16bit Passive Parallel
  160. */
  161. /*
  162. * cd ratio is dependent on cfg width and whether the bitstream
  163. * is encrypted and/or compressed.
  164. *
  165. * | width | encr. | compr. | cd ratio |
  166. * | 16 | 0 | 0 | 1 |
  167. * | 16 | 0 | 1 | 4 |
  168. * | 16 | 1 | 0 | 2 |
  169. * | 16 | 1 | 1 | 4 |
  170. * | 32 | 0 | 0 | 1 |
  171. * | 32 | 0 | 1 | 8 |
  172. * | 32 | 1 | 0 | 4 |
  173. * | 32 | 1 | 1 | 8 |
  174. */
  175. if (!compress && !encrypt) {
  176. cd_ratio = CDRATIO_x1;
  177. } else {
  178. if (compress)
  179. cd_ratio = CDRATIO_x4;
  180. else
  181. cd_ratio = CDRATIO_x2;
  182. /* if 32 bit, double the cd ratio (so register
  183. field setting is incremented) */
  184. if (cfg_width == CFGWDTH_32)
  185. cd_ratio += 1;
  186. }
  187. fpgamgr_set_cfgwdth(cfg_width);
  188. fpgamgr_set_cd_ratio(cd_ratio);
  189. return 0;
  190. }
  191. static int fpgamgr_reset(void)
  192. {
  193. unsigned long reg;
  194. /* S2F_NCONFIG = 0 */
  195. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  196. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  197. /* Wait for f2s_nstatus == 0 */
  198. if (wait_for_f2s_nstatus_pin(0))
  199. return -ETIME;
  200. /* S2F_NCONFIG = 1 */
  201. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  202. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  203. /* Wait for f2s_nstatus == 1 */
  204. if (wait_for_f2s_nstatus_pin(1))
  205. return -ETIME;
  206. /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
  207. reg = readl(&fpga_manager_base->imgcfg_stat);
  208. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
  209. return -EPERM;
  210. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
  211. return -EPERM;
  212. return 0;
  213. }
  214. /* Start the FPGA programming by initialize the FPGA Manager */
  215. int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
  216. {
  217. int ret;
  218. /* Step 1 */
  219. if (fpgamgr_verify_msel())
  220. return -EPERM;
  221. /* Step 2 */
  222. if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
  223. return -EPERM;
  224. /*
  225. * Step 3:
  226. * Make sure no other external devices are trying to interfere with
  227. * programming:
  228. */
  229. if (wait_for_nconfig_pin_and_nstatus_pin())
  230. return -ETIME;
  231. /*
  232. * Step 4:
  233. * Deassert the signal drives from HPS
  234. *
  235. * S2F_NCE = 1
  236. * S2F_PR_REQUEST = 0
  237. * EN_CFG_CTRL = 0
  238. * EN_CFG_DATA = 0
  239. * S2F_NCONFIG = 1
  240. * S2F_NSTATUS_OE = 0
  241. * S2F_CONDONE_OE = 0
  242. */
  243. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  244. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  245. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  246. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
  247. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  248. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  249. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  250. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  251. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
  252. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  253. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
  254. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
  255. /*
  256. * Step 5:
  257. * Enable overrides
  258. * S2F_NENABLE_CONFIG = 0
  259. * S2F_NENABLE_NCONFIG = 0
  260. */
  261. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  262. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  263. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  264. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  265. /*
  266. * Disable driving signals that HPS doesn't need to drive.
  267. * S2F_NENABLE_NSTATUS = 1
  268. * S2F_NENABLE_CONDONE = 1
  269. */
  270. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  271. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
  272. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
  273. /*
  274. * Step 6:
  275. * Drive chip select S2F_NCE = 0
  276. */
  277. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  278. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  279. /* Step 7 */
  280. if (wait_for_nconfig_pin_and_nstatus_pin())
  281. return -ETIME;
  282. /* Step 8 */
  283. ret = fpgamgr_reset();
  284. if (ret)
  285. return ret;
  286. /*
  287. * Step 9:
  288. * EN_CFG_CTRL and EN_CFG_DATA = 1
  289. */
  290. setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  291. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  292. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  293. return 0;
  294. }
  295. /* Ensure the FPGA entering config done */
  296. static int fpgamgr_program_poll_cd(void)
  297. {
  298. unsigned long reg, i;
  299. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  300. reg = readl(&fpga_manager_base->imgcfg_stat);
  301. if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
  302. return 0;
  303. if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
  304. printf("nstatus == 0 while waiting for condone\n");
  305. return -EPERM;
  306. }
  307. WATCHDOG_RESET();
  308. }
  309. if (i == FPGA_TIMEOUT_CNT)
  310. return -ETIME;
  311. return 0;
  312. }
  313. /* Ensure the FPGA entering user mode */
  314. static int fpgamgr_program_poll_usermode(void)
  315. {
  316. unsigned long reg;
  317. int ret = 0;
  318. if (fpgamgr_dclkcnt_set(0xf))
  319. return -ETIME;
  320. ret = wait_for_user_mode();
  321. if (ret < 0) {
  322. printf("%s: Failed to enter user mode with ", __func__);
  323. printf("error code %d\n", ret);
  324. return ret;
  325. }
  326. /*
  327. * Step 14:
  328. * Stop DATA path and Dclk
  329. * EN_CFG_CTRL and EN_CFG_DATA = 0
  330. */
  331. clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
  332. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
  333. ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
  334. /*
  335. * Step 15:
  336. * Disable overrides
  337. * S2F_NENABLE_CONFIG = 1
  338. * S2F_NENABLE_NCONFIG = 1
  339. */
  340. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  341. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
  342. setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
  343. ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
  344. /* Disable chip select S2F_NCE = 1 */
  345. setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
  346. ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
  347. /*
  348. * Step 16:
  349. * Final check
  350. */
  351. reg = readl(&fpga_manager_base->imgcfg_stat);
  352. if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
  353. ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
  354. ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
  355. ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
  356. ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
  357. ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
  358. return -EPERM;
  359. return 0;
  360. }
  361. int fpgamgr_program_finish(void)
  362. {
  363. /* Ensure the FPGA entering config done */
  364. int status = fpgamgr_program_poll_cd();
  365. if (status) {
  366. printf("FPGA: Poll CD failed with error code %d\n", status);
  367. return -EPERM;
  368. }
  369. /* Ensure the FPGA entering user mode */
  370. status = fpgamgr_program_poll_usermode();
  371. if (status) {
  372. printf("FPGA: Poll usermode failed with error code %d\n",
  373. status);
  374. return -EPERM;
  375. }
  376. printf("Full Configuration Succeeded.\n");
  377. return 0;
  378. }
  379. ofnode get_fpga_mgr_ofnode(ofnode from)
  380. {
  381. return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
  382. }
  383. const char *get_fpga_filename(void)
  384. {
  385. const char *fpga_filename = NULL;
  386. ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
  387. if (ofnode_valid(fpgamgr_node))
  388. fpga_filename = ofnode_read_string(fpgamgr_node,
  389. "altr,bitstream");
  390. return fpga_filename;
  391. }
  392. static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
  393. {
  394. /*
  395. * Magic ID starting at:
  396. * -> 1st dword[15:0] in periph.rbf
  397. * -> 2nd dword[15:0] in core.rbf
  398. * Note: dword == 32 bits
  399. */
  400. u32 word_reading_max = 2;
  401. u32 i;
  402. for (i = 0; i < word_reading_max; i++) {
  403. if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
  404. rbf->security = unencrypted;
  405. } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
  406. rbf->security = encrypted;
  407. } else if (*(buffer + i + 1) ==
  408. FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
  409. rbf->security = unencrypted;
  410. } else if (*(buffer + i + 1) ==
  411. FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
  412. rbf->security = encrypted;
  413. } else {
  414. rbf->security = invalid;
  415. continue;
  416. }
  417. /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
  418. if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
  419. rbf->section = periph_section;
  420. break;
  421. } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
  422. rbf->section = core_section;
  423. break;
  424. } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
  425. rbf->section = periph_section;
  426. break;
  427. } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
  428. rbf->section = core_section;
  429. break;
  430. }
  431. rbf->section = unknown;
  432. break;
  433. WATCHDOG_RESET();
  434. }
  435. }
  436. #ifdef CONFIG_FS_LOADER
  437. static int first_loading_rbf_to_buffer(struct udevice *dev,
  438. struct fpga_loadfs_info *fpga_loadfs,
  439. u32 *buffer, size_t *buffer_bsize)
  440. {
  441. u32 *buffer_p = (u32 *)*buffer;
  442. u32 *loadable = buffer_p;
  443. size_t buffer_size = *buffer_bsize;
  444. size_t fit_size;
  445. int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
  446. const char *fpga_node_name = NULL;
  447. const char *uname = NULL;
  448. /* Load image header into buffer */
  449. ret = request_firmware_into_buf(dev,
  450. fpga_loadfs->fpga_fsinfo->filename,
  451. buffer_p, sizeof(struct image_header),
  452. 0);
  453. if (ret < 0) {
  454. debug("FPGA: Failed to read image header from flash.\n");
  455. return -ENOENT;
  456. }
  457. if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
  458. debug("FPGA: No FDT magic was found.\n");
  459. return -EBADF;
  460. }
  461. fit_size = fdt_totalsize(buffer_p);
  462. if (fit_size > buffer_size) {
  463. debug("FPGA: FIT image is larger than available buffer.\n");
  464. debug("Please use FIT external data or increasing buffer.\n");
  465. return -ENOMEM;
  466. }
  467. /* Load entire FIT into buffer */
  468. ret = request_firmware_into_buf(dev,
  469. fpga_loadfs->fpga_fsinfo->filename,
  470. buffer_p, fit_size, 0);
  471. if (ret < 0)
  472. return ret;
  473. ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
  474. if (ret) {
  475. debug("FPGA: No valid FIT image was found.\n");
  476. return ret;
  477. }
  478. confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
  479. images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
  480. if (confs_noffset < 0 || images_noffset < 0) {
  481. debug("FPGA: No Configurations or images nodes were found.\n");
  482. return -ENOENT;
  483. }
  484. /* Get default configuration unit name from default property */
  485. confs_noffset = fit_conf_get_node(buffer_p, NULL);
  486. if (confs_noffset < 0) {
  487. debug("FPGA: No default configuration was found in config.\n");
  488. return -ENOENT;
  489. }
  490. count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
  491. FIT_FPGA_PROP);
  492. if (count < 0) {
  493. debug("FPGA: Invalid configuration format for FPGA node.\n");
  494. return count;
  495. }
  496. debug("FPGA: FPGA node count: %d\n", count);
  497. for (i = 0; i < count; i++) {
  498. images_noffset = fit_conf_get_prop_node_index(buffer_p,
  499. confs_noffset,
  500. FIT_FPGA_PROP, i);
  501. uname = fit_get_name(buffer_p, images_noffset, NULL);
  502. if (uname) {
  503. debug("FPGA: %s\n", uname);
  504. if (strstr(uname, "fpga-periph") &&
  505. (!is_fpgamgr_early_user_mode() ||
  506. is_fpgamgr_user_mode())) {
  507. fpga_node_name = uname;
  508. printf("FPGA: Start to program ");
  509. printf("peripheral/full bitstream ...\n");
  510. break;
  511. } else if (strstr(uname, "fpga-core") &&
  512. (is_fpgamgr_early_user_mode() &&
  513. !is_fpgamgr_user_mode())) {
  514. fpga_node_name = uname;
  515. printf("FPGA: Start to program core ");
  516. printf("bitstream ...\n");
  517. break;
  518. }
  519. }
  520. WATCHDOG_RESET();
  521. }
  522. if (!fpga_node_name) {
  523. debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
  524. return 1;
  525. }
  526. images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
  527. if (images_noffset < 0) {
  528. debug("FPGA: No node '%s' was found in FIT.\n",
  529. fpga_node_name);
  530. return -ENOENT;
  531. }
  532. if (!fit_image_get_data_position(buffer_p, images_noffset,
  533. &rbf_offset)) {
  534. debug("FPGA: Data position was found.\n");
  535. } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
  536. &rbf_offset)) {
  537. /*
  538. * For FIT with external data, figure out where
  539. * the external images start. This is the base
  540. * for the data-offset properties in each image.
  541. */
  542. rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
  543. debug("FPGA: Data offset was found.\n");
  544. } else {
  545. debug("FPGA: No data position/offset was found.\n");
  546. return -ENOENT;
  547. }
  548. ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
  549. if (ret < 0) {
  550. debug("FPGA: No data size was found (err=%d).\n", ret);
  551. return -ENOENT;
  552. }
  553. if (gd->ram_size < rbf_size) {
  554. debug("FPGA: Using default OCRAM buffer and size.\n");
  555. } else {
  556. ret = fit_image_get_load(buffer_p, images_noffset,
  557. (ulong *)loadable);
  558. if (ret < 0) {
  559. buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
  560. debug("FPGA: No loadable was found.\n");
  561. debug("FPGA: Using default DDR load address: 0x%x .\n",
  562. DEFAULT_DDR_LOAD_ADDRESS);
  563. } else {
  564. buffer_p = (u32 *)*loadable;
  565. debug("FPGA: Found loadable address = 0x%x.\n",
  566. *loadable);
  567. }
  568. buffer_size = rbf_size;
  569. }
  570. debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
  571. rbf_offset, rbf_size);
  572. fpga_loadfs->remaining = rbf_size;
  573. /*
  574. * Determine buffer size vs bitstream size, and calculating number of
  575. * chunk by chunk transfer is required due to smaller buffer size
  576. * compare to bitstream
  577. */
  578. if (rbf_size <= buffer_size) {
  579. /* Loading whole bitstream into buffer */
  580. buffer_size = rbf_size;
  581. fpga_loadfs->remaining = 0;
  582. } else {
  583. fpga_loadfs->remaining -= buffer_size;
  584. }
  585. fpga_loadfs->offset = rbf_offset;
  586. /* Loading bitstream into buffer */
  587. ret = request_firmware_into_buf(dev,
  588. fpga_loadfs->fpga_fsinfo->filename,
  589. buffer_p, buffer_size,
  590. fpga_loadfs->offset);
  591. if (ret < 0) {
  592. debug("FPGA: Failed to read bitstream from flash.\n");
  593. return -ENOENT;
  594. }
  595. /* Getting info about bitstream types */
  596. get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
  597. /* Update next reading bitstream offset */
  598. fpga_loadfs->offset += buffer_size;
  599. /* Update the final addr for bitstream */
  600. *buffer = (u32)buffer_p;
  601. /* Update the size of bitstream to be programmed into FPGA */
  602. *buffer_bsize = buffer_size;
  603. return 0;
  604. }
  605. static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
  606. struct fpga_loadfs_info *fpga_loadfs,
  607. u32 *buffer, size_t *buffer_bsize)
  608. {
  609. int ret = 0;
  610. u32 *buffer_p = (u32 *)*buffer;
  611. /* Read the bitstream chunk by chunk. */
  612. if (fpga_loadfs->remaining > *buffer_bsize) {
  613. fpga_loadfs->remaining -= *buffer_bsize;
  614. } else {
  615. *buffer_bsize = fpga_loadfs->remaining;
  616. fpga_loadfs->remaining = 0;
  617. }
  618. ret = request_firmware_into_buf(dev,
  619. fpga_loadfs->fpga_fsinfo->filename,
  620. buffer_p, *buffer_bsize,
  621. fpga_loadfs->offset);
  622. if (ret < 0) {
  623. debug("FPGA: Failed to read bitstream from flash.\n");
  624. return -ENOENT;
  625. }
  626. /* Update next reading bitstream offset */
  627. fpga_loadfs->offset += *buffer_bsize;
  628. return 0;
  629. }
  630. int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
  631. u32 offset)
  632. {
  633. struct fpga_loadfs_info fpga_loadfs;
  634. struct udevice *dev;
  635. int status, ret, size;
  636. u32 buffer = (uintptr_t)buf;
  637. size_t buffer_sizebytes = bsize;
  638. size_t buffer_sizebytes_ori = bsize;
  639. size_t total_sizeof_image = 0;
  640. ofnode node;
  641. const fdt32_t *phandle_p;
  642. u32 phandle;
  643. node = get_fpga_mgr_ofnode(ofnode_null());
  644. if (ofnode_valid(node)) {
  645. phandle_p = ofnode_get_property(node, "firmware-loader", &size);
  646. if (!phandle_p) {
  647. node = ofnode_path("/chosen");
  648. if (!ofnode_valid(node)) {
  649. debug("FPGA: /chosen node was not found.\n");
  650. return -ENOENT;
  651. }
  652. phandle_p = ofnode_get_property(node, "firmware-loader",
  653. &size);
  654. if (!phandle_p) {
  655. debug("FPGA: firmware-loader property was not");
  656. debug(" found.\n");
  657. return -ENOENT;
  658. }
  659. }
  660. } else {
  661. debug("FPGA: FPGA manager node was not found.\n");
  662. return -ENOENT;
  663. }
  664. phandle = fdt32_to_cpu(*phandle_p);
  665. ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
  666. phandle, &dev);
  667. if (ret)
  668. return ret;
  669. memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
  670. fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
  671. fpga_loadfs.offset = offset;
  672. printf("FPGA: Checking FPGA configuration setting ...\n");
  673. /*
  674. * Note: Both buffer and buffer_sizebytes values can be altered by
  675. * function below.
  676. */
  677. ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
  678. &buffer_sizebytes);
  679. if (ret == 1) {
  680. printf("FPGA: Skipping configuration ...\n");
  681. return 0;
  682. } else if (ret) {
  683. return ret;
  684. }
  685. if (fpga_loadfs.rbfinfo.section == core_section &&
  686. !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
  687. debug("FPGA : Must be in Early Release mode to program ");
  688. debug("core bitstream.\n");
  689. return -EPERM;
  690. }
  691. /* Disable all signals from HPS peripheral controller to FPGA */
  692. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
  693. /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
  694. socfpga_bridges_reset();
  695. if (fpga_loadfs.rbfinfo.section == periph_section) {
  696. /* Initialize the FPGA Manager */
  697. status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
  698. if (status) {
  699. debug("FPGA: Init with peripheral bitstream failed.\n");
  700. return -EPERM;
  701. }
  702. }
  703. /* Transfer bitstream to FPGA Manager */
  704. fpgamgr_program_write((void *)buffer, buffer_sizebytes);
  705. total_sizeof_image += buffer_sizebytes;
  706. while (fpga_loadfs.remaining) {
  707. ret = subsequent_loading_rbf_to_buffer(dev,
  708. &fpga_loadfs,
  709. &buffer,
  710. &buffer_sizebytes_ori);
  711. if (ret)
  712. return ret;
  713. /* Transfer data to FPGA Manager */
  714. fpgamgr_program_write((void *)buffer,
  715. buffer_sizebytes_ori);
  716. total_sizeof_image += buffer_sizebytes_ori;
  717. WATCHDOG_RESET();
  718. }
  719. if (fpga_loadfs.rbfinfo.section == periph_section) {
  720. if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
  721. config_pins(gd->fdt_blob, "shared");
  722. puts("FPGA: Early Release Succeeded.\n");
  723. } else {
  724. debug("FPGA: Failed to see Early Release.\n");
  725. return -EIO;
  726. }
  727. /* For monolithic bitstream */
  728. if (is_fpgamgr_user_mode()) {
  729. /* Ensure the FPGA entering config done */
  730. status = fpgamgr_program_finish();
  731. if (status)
  732. return status;
  733. config_pins(gd->fdt_blob, "fpga");
  734. puts("FPGA: Enter user mode.\n");
  735. }
  736. } else if (fpga_loadfs.rbfinfo.section == core_section) {
  737. /* Ensure the FPGA entering config done */
  738. status = fpgamgr_program_finish();
  739. if (status)
  740. return status;
  741. config_pins(gd->fdt_blob, "fpga");
  742. puts("FPGA: Enter user mode.\n");
  743. } else {
  744. debug("FPGA: Config Error: Unsupported bitstream type.\n");
  745. return -ENOEXEC;
  746. }
  747. return (int)total_sizeof_image;
  748. }
  749. void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
  750. {
  751. fpga_fs_info fpga_fsinfo;
  752. fpga_fsinfo.filename = get_fpga_filename();
  753. if (fpga_fsinfo.filename)
  754. socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
  755. }
  756. #endif
  757. /* This function is used to load the core bitstream from the OCRAM. */
  758. int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  759. {
  760. unsigned long status;
  761. struct rbf_info rbfinfo;
  762. memset(&rbfinfo, 0, sizeof(rbfinfo));
  763. /* Disable all signals from hps peripheral controller to fpga */
  764. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
  765. /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
  766. socfpga_bridges_reset();
  767. /* Getting info about bitstream types */
  768. get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
  769. if (rbfinfo.section == periph_section) {
  770. /* Initialize the FPGA Manager */
  771. status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
  772. if (status)
  773. return status;
  774. }
  775. if (rbfinfo.section == core_section &&
  776. !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
  777. debug("FPGA : Must be in early release mode to program ");
  778. debug("core bitstream.\n");
  779. return -EPERM;
  780. }
  781. /* Write the bitstream to FPGA Manager */
  782. fpgamgr_program_write(rbf_data, rbf_size);
  783. status = fpgamgr_program_finish();
  784. if (status)
  785. return status;
  786. config_pins(gd->fdt_blob, "fpga");
  787. puts("FPGA: Enter user mode.\n");
  788. return status;
  789. }