mmc.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/list.h>
  11. #include <linux/sizes.h>
  12. #include <linux/compiler.h>
  13. #include <linux/dma-direction.h>
  14. #include <part.h>
  15. struct bd_info;
  16. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  17. #define MMC_SUPPORTS_TUNING
  18. #endif
  19. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  20. #define MMC_SUPPORTS_TUNING
  21. #endif
  22. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  23. #define SD_VERSION_SD (1U << 31)
  24. #define MMC_VERSION_MMC (1U << 30)
  25. #define MAKE_SDMMC_VERSION(a, b, c) \
  26. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  27. #define MAKE_SD_VERSION(a, b, c) \
  28. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  29. #define MAKE_MMC_VERSION(a, b, c) \
  30. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  31. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  32. (((u32)(x) >> 16) & 0xff)
  33. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  34. (((u32)(x) >> 8) & 0xff)
  35. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  36. ((u32)(x) & 0xff)
  37. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  38. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  39. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  40. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  41. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  42. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  43. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  44. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  45. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  46. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  47. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  48. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  49. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  50. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  51. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  52. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  53. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  54. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  55. #define MMC_CAP(mode) (1 << mode)
  56. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  57. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  58. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  59. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  60. #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
  61. #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
  62. #define MMC_CAP_NONREMOVABLE BIT(14)
  63. #define MMC_CAP_NEEDS_POLL BIT(15)
  64. #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
  65. #define MMC_MODE_8BIT BIT(30)
  66. #define MMC_MODE_4BIT BIT(29)
  67. #define MMC_MODE_1BIT BIT(28)
  68. #define MMC_MODE_SPI BIT(27)
  69. #define SD_DATA_4BIT 0x00040000
  70. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  71. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  72. #define MMC_DATA_READ 1
  73. #define MMC_DATA_WRITE 2
  74. #define MMC_CMD_GO_IDLE_STATE 0
  75. #define MMC_CMD_SEND_OP_COND 1
  76. #define MMC_CMD_ALL_SEND_CID 2
  77. #define MMC_CMD_SET_RELATIVE_ADDR 3
  78. #define MMC_CMD_SET_DSR 4
  79. #define MMC_CMD_SWITCH 6
  80. #define MMC_CMD_SELECT_CARD 7
  81. #define MMC_CMD_SEND_EXT_CSD 8
  82. #define MMC_CMD_SEND_CSD 9
  83. #define MMC_CMD_SEND_CID 10
  84. #define MMC_CMD_STOP_TRANSMISSION 12
  85. #define MMC_CMD_SEND_STATUS 13
  86. #define MMC_CMD_SET_BLOCKLEN 16
  87. #define MMC_CMD_READ_SINGLE_BLOCK 17
  88. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  89. #define MMC_CMD_SEND_TUNING_BLOCK 19
  90. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  91. #define MMC_CMD_SET_BLOCK_COUNT 23
  92. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  93. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  94. #define MMC_CMD_ERASE_GROUP_START 35
  95. #define MMC_CMD_ERASE_GROUP_END 36
  96. #define MMC_CMD_ERASE 38
  97. #define MMC_CMD_APP_CMD 55
  98. #define MMC_CMD_SPI_READ_OCR 58
  99. #define MMC_CMD_SPI_CRC_ON_OFF 59
  100. #define MMC_CMD_RES_MAN 62
  101. #define MMC_CMD62_ARG1 0xefac62ec
  102. #define MMC_CMD62_ARG2 0xcbaea7
  103. #define SD_CMD_SEND_RELATIVE_ADDR 3
  104. #define SD_CMD_SWITCH_FUNC 6
  105. #define SD_CMD_SEND_IF_COND 8
  106. #define SD_CMD_SWITCH_UHS18V 11
  107. #define SD_CMD_APP_SET_BUS_WIDTH 6
  108. #define SD_CMD_APP_SD_STATUS 13
  109. #define SD_CMD_ERASE_WR_BLK_START 32
  110. #define SD_CMD_ERASE_WR_BLK_END 33
  111. #define SD_CMD_APP_SEND_OP_COND 41
  112. #define SD_CMD_APP_SEND_SCR 51
  113. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  114. {
  115. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  116. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  117. return true;
  118. return false;
  119. }
  120. /* SCR definitions in different words */
  121. #define SD_HIGHSPEED_BUSY 0x00020000
  122. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  123. #define UHS_SDR12_BUS_SPEED 0
  124. #define HIGH_SPEED_BUS_SPEED 1
  125. #define UHS_SDR25_BUS_SPEED 1
  126. #define UHS_SDR50_BUS_SPEED 2
  127. #define UHS_SDR104_BUS_SPEED 3
  128. #define UHS_DDR50_BUS_SPEED 4
  129. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  130. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  131. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  132. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  133. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  134. #define OCR_BUSY 0x80000000
  135. #define OCR_HCS 0x40000000
  136. #define OCR_S18R 0x1000000
  137. #define OCR_VOLTAGE_MASK 0x007FFF80
  138. #define OCR_ACCESS_MODE 0x60000000
  139. #define MMC_ERASE_ARG 0x00000000
  140. #define MMC_SECURE_ERASE_ARG 0x80000000
  141. #define MMC_TRIM_ARG 0x00000001
  142. #define MMC_DISCARD_ARG 0x00000003
  143. #define MMC_SECURE_TRIM1_ARG 0x80000001
  144. #define MMC_SECURE_TRIM2_ARG 0x80008000
  145. #define MMC_STATUS_MASK (~0x0206BF7F)
  146. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  147. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  148. #define MMC_STATUS_CURR_STATE (0xf << 9)
  149. #define MMC_STATUS_ERROR (1 << 19)
  150. #define MMC_STATE_PRG (7 << 9)
  151. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  152. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  153. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  154. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  155. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  156. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  157. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  158. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  159. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  160. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  161. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  162. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  163. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  164. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  165. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  166. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  167. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  168. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  169. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  170. addressed by index which are
  171. 1 in value field */
  172. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  173. addressed by index, which are
  174. 1 in value field */
  175. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  176. #define SD_SWITCH_CHECK 0
  177. #define SD_SWITCH_SWITCH 1
  178. /*
  179. * EXT_CSD fields
  180. */
  181. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  182. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  183. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  184. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  185. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  186. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  187. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  188. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  189. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  190. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  191. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  192. #define EXT_CSD_RPMB_MULT 168 /* RO */
  193. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  194. #define EXT_CSD_BOOT_BUS_WIDTH 177
  195. #define EXT_CSD_PART_CONF 179 /* R/W */
  196. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  197. #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
  198. #define EXT_CSD_HS_TIMING 185 /* R/W */
  199. #define EXT_CSD_REV 192 /* RO */
  200. #define EXT_CSD_CARD_TYPE 196 /* RO */
  201. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  202. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  203. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  204. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  205. #define EXT_CSD_BOOT_MULT 226 /* RO */
  206. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  207. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  208. /*
  209. * EXT_CSD field definitions
  210. */
  211. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  212. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  213. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  214. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  215. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  216. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  217. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  218. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  219. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  220. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  221. /* SDR mode @1.8V I/O */
  222. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  223. /* SDR mode @1.2V I/O */
  224. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  225. EXT_CSD_CARD_TYPE_HS200_1_2V)
  226. #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
  227. #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
  228. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  229. EXT_CSD_CARD_TYPE_HS400_1_2V)
  230. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  231. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  232. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  233. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  234. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  235. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  236. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  237. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  238. #define EXT_CSD_TIMING_HS 1 /* HS */
  239. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  240. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  241. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  242. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  243. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  244. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  245. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  246. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  247. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  248. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  249. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  250. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  251. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  252. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  253. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  254. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  255. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  256. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  257. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  258. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  259. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  260. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  261. #define R1_ILLEGAL_COMMAND (1 << 22)
  262. #define R1_APP_CMD (1 << 5)
  263. #define MMC_RSP_PRESENT (1 << 0)
  264. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  265. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  266. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  267. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  268. #define MMC_RSP_NONE (0)
  269. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  270. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  271. MMC_RSP_BUSY)
  272. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  273. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  274. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  275. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  276. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  277. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  278. #define MMCPART_NOAVAILABLE (0xff)
  279. #define PART_ACCESS_MASK (0x7)
  280. #define PART_SUPPORT (0x1)
  281. #define ENHNCD_SUPPORT (0x2)
  282. #define PART_ENH_ATTRIB (0x1f)
  283. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  284. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  285. #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
  286. enum mmc_voltage {
  287. MMC_SIGNAL_VOLTAGE_000 = 0,
  288. MMC_SIGNAL_VOLTAGE_120 = 1,
  289. MMC_SIGNAL_VOLTAGE_180 = 2,
  290. MMC_SIGNAL_VOLTAGE_330 = 4,
  291. };
  292. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  293. MMC_SIGNAL_VOLTAGE_180 |\
  294. MMC_SIGNAL_VOLTAGE_330)
  295. /* Maximum block size for MMC */
  296. #define MMC_MAX_BLOCK_LEN 512
  297. /* The number of MMC physical partitions. These consist of:
  298. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  299. */
  300. #define MMC_NUM_BOOT_PARTITION 2
  301. #define MMC_PART_RPMB 3 /* RPMB partition number */
  302. /* Driver model support */
  303. /**
  304. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  305. */
  306. struct mmc_uclass_priv {
  307. struct mmc *mmc;
  308. };
  309. /**
  310. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  311. *
  312. * Provided that the device is already probed and ready for use, this value
  313. * will be available.
  314. *
  315. * @dev: Device
  316. * @return associated mmc struct pointer if available, else NULL
  317. */
  318. struct mmc *mmc_get_mmc_dev(struct udevice *dev);
  319. /* End of driver model support */
  320. struct mmc_cid {
  321. unsigned long psn;
  322. unsigned short oid;
  323. unsigned char mid;
  324. unsigned char prv;
  325. unsigned char mdt;
  326. char pnm[7];
  327. };
  328. struct mmc_cmd {
  329. ushort cmdidx;
  330. uint resp_type;
  331. uint cmdarg;
  332. uint response[4];
  333. };
  334. struct mmc_data {
  335. union {
  336. char *dest;
  337. const char *src; /* src buffers don't get written to */
  338. };
  339. uint flags;
  340. uint blocks;
  341. uint blocksize;
  342. };
  343. /* forward decl. */
  344. struct mmc;
  345. #if CONFIG_IS_ENABLED(DM_MMC)
  346. struct dm_mmc_ops {
  347. /**
  348. * deferred_probe() - Some configurations that need to be deferred
  349. * to just before enumerating the device
  350. *
  351. * @dev: Device to init
  352. * @return 0 if Ok, -ve if error
  353. */
  354. int (*deferred_probe)(struct udevice *dev);
  355. /**
  356. * send_cmd() - Send a command to the MMC device
  357. *
  358. * @dev: Device to receive the command
  359. * @cmd: Command to send
  360. * @data: Additional data to send/receive
  361. * @return 0 if OK, -ve on error
  362. */
  363. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  364. struct mmc_data *data);
  365. /**
  366. * set_ios() - Set the I/O speed/width for an MMC device
  367. *
  368. * @dev: Device to update
  369. * @return 0 if OK, -ve on error
  370. */
  371. int (*set_ios)(struct udevice *dev);
  372. /**
  373. * get_cd() - See whether a card is present
  374. *
  375. * @dev: Device to check
  376. * @return 0 if not present, 1 if present, -ve on error
  377. */
  378. int (*get_cd)(struct udevice *dev);
  379. /**
  380. * get_wp() - See whether a card has write-protect enabled
  381. *
  382. * @dev: Device to check
  383. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  384. */
  385. int (*get_wp)(struct udevice *dev);
  386. #ifdef MMC_SUPPORTS_TUNING
  387. /**
  388. * execute_tuning() - Start the tuning process
  389. *
  390. * @dev: Device to start the tuning
  391. * @opcode: Command opcode to send
  392. * @return 0 if OK, -ve on error
  393. */
  394. int (*execute_tuning)(struct udevice *dev, uint opcode);
  395. #endif
  396. /**
  397. * wait_dat0() - wait until dat0 is in the target state
  398. * (CLK must be running during the wait)
  399. *
  400. * @dev: Device to check
  401. * @state: target state
  402. * @timeout_us: timeout in us
  403. * @return 0 if dat0 is in the target state, -ve on error
  404. */
  405. int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
  406. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  407. /* set_enhanced_strobe() - set HS400 enhanced strobe */
  408. int (*set_enhanced_strobe)(struct udevice *dev);
  409. #endif
  410. /**
  411. * host_power_cycle - host specific tasks in power cycle sequence
  412. * Called between mmc_power_off() and
  413. * mmc_power_on()
  414. *
  415. * @dev: Device to check
  416. * @return 0 if not present, 1 if present, -ve on error
  417. */
  418. int (*host_power_cycle)(struct udevice *dev);
  419. };
  420. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  421. int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  422. struct mmc_data *data);
  423. int dm_mmc_set_ios(struct udevice *dev);
  424. int dm_mmc_get_cd(struct udevice *dev);
  425. int dm_mmc_get_wp(struct udevice *dev);
  426. int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
  427. int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
  428. int dm_mmc_host_power_cycle(struct udevice *dev);
  429. int dm_mmc_deferred_probe(struct udevice *dev);
  430. /* Transition functions for compatibility */
  431. int mmc_set_ios(struct mmc *mmc);
  432. int mmc_getcd(struct mmc *mmc);
  433. int mmc_getwp(struct mmc *mmc);
  434. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  435. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
  436. int mmc_set_enhanced_strobe(struct mmc *mmc);
  437. int mmc_host_power_cycle(struct mmc *mmc);
  438. int mmc_deferred_probe(struct mmc *mmc);
  439. #else
  440. struct mmc_ops {
  441. int (*send_cmd)(struct mmc *mmc,
  442. struct mmc_cmd *cmd, struct mmc_data *data);
  443. int (*set_ios)(struct mmc *mmc);
  444. int (*init)(struct mmc *mmc);
  445. int (*getcd)(struct mmc *mmc);
  446. int (*getwp)(struct mmc *mmc);
  447. int (*host_power_cycle)(struct mmc *mmc);
  448. };
  449. #endif
  450. struct mmc_config {
  451. const char *name;
  452. #if !CONFIG_IS_ENABLED(DM_MMC)
  453. const struct mmc_ops *ops;
  454. #endif
  455. uint host_caps;
  456. uint voltages;
  457. uint f_min;
  458. uint f_max;
  459. uint b_max;
  460. unsigned char part_type;
  461. };
  462. struct sd_ssr {
  463. unsigned int au; /* In sectors */
  464. unsigned int erase_timeout; /* In milliseconds */
  465. unsigned int erase_offset; /* In milliseconds */
  466. };
  467. enum bus_mode {
  468. MMC_LEGACY,
  469. MMC_HS,
  470. SD_HS,
  471. MMC_HS_52,
  472. MMC_DDR_52,
  473. UHS_SDR12,
  474. UHS_SDR25,
  475. UHS_SDR50,
  476. UHS_DDR50,
  477. UHS_SDR104,
  478. MMC_HS_200,
  479. MMC_HS_400,
  480. MMC_HS_400_ES,
  481. MMC_MODES_END
  482. };
  483. const char *mmc_mode_name(enum bus_mode mode);
  484. void mmc_dump_capabilities(const char *text, uint caps);
  485. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  486. {
  487. if (mode == MMC_DDR_52)
  488. return true;
  489. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  490. else if (mode == UHS_DDR50)
  491. return true;
  492. #endif
  493. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  494. else if (mode == MMC_HS_400)
  495. return true;
  496. #endif
  497. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  498. else if (mode == MMC_HS_400_ES)
  499. return true;
  500. #endif
  501. else
  502. return false;
  503. }
  504. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  505. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  506. MMC_CAP(UHS_DDR50))
  507. static inline bool supports_uhs(uint caps)
  508. {
  509. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  510. return (caps & UHS_CAPS) ? true : false;
  511. #else
  512. return false;
  513. #endif
  514. }
  515. /*
  516. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  517. * with mmc_get_mmc_dev().
  518. *
  519. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  520. */
  521. struct mmc {
  522. #if !CONFIG_IS_ENABLED(BLK)
  523. struct list_head link;
  524. #endif
  525. const struct mmc_config *cfg; /* provided configuration */
  526. uint version;
  527. void *priv;
  528. uint has_init;
  529. int high_capacity;
  530. bool clk_disable; /* true if the clock can be turned off */
  531. uint bus_width;
  532. uint clock;
  533. uint saved_clock;
  534. enum mmc_voltage signal_voltage;
  535. uint card_caps;
  536. uint host_caps;
  537. uint ocr;
  538. uint dsr;
  539. uint dsr_imp;
  540. uint scr[2];
  541. uint csd[4];
  542. uint cid[4];
  543. ushort rca;
  544. u8 part_support;
  545. u8 part_attr;
  546. u8 wr_rel_set;
  547. u8 part_config;
  548. u8 gen_cmd6_time; /* units: 10 ms */
  549. u8 part_switch_time; /* units: 10 ms */
  550. uint tran_speed;
  551. uint legacy_speed; /* speed for the legacy mode provided by the card */
  552. uint read_bl_len;
  553. #if CONFIG_IS_ENABLED(MMC_WRITE)
  554. uint write_bl_len;
  555. uint erase_grp_size; /* in 512-byte sectors */
  556. #endif
  557. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  558. uint hc_wp_grp_size; /* in 512-byte sectors */
  559. #endif
  560. #if CONFIG_IS_ENABLED(MMC_WRITE)
  561. struct sd_ssr ssr; /* SD status register */
  562. #endif
  563. u64 capacity;
  564. u64 capacity_user;
  565. u64 capacity_boot;
  566. u64 capacity_rpmb;
  567. u64 capacity_gp[4];
  568. #ifndef CONFIG_SPL_BUILD
  569. u64 enh_user_start;
  570. u64 enh_user_size;
  571. #endif
  572. #if !CONFIG_IS_ENABLED(BLK)
  573. struct blk_desc block_dev;
  574. #endif
  575. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  576. char init_in_progress; /* 1 if we have done mmc_start_init() */
  577. char preinit; /* start init as early as possible */
  578. int ddr_mode;
  579. #if CONFIG_IS_ENABLED(DM_MMC)
  580. struct udevice *dev; /* Device for this MMC controller */
  581. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  582. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  583. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  584. #endif
  585. #endif
  586. u8 *ext_csd;
  587. u32 cardtype; /* cardtype read from the MMC */
  588. enum mmc_voltage current_voltage;
  589. enum bus_mode selected_mode; /* mode currently used */
  590. enum bus_mode best_mode; /* best mode is the supported mode with the
  591. * highest bandwidth. It may not always be the
  592. * operating mode due to limitations when
  593. * accessing the boot partitions
  594. */
  595. u32 quirks;
  596. };
  597. struct mmc_hwpart_conf {
  598. struct {
  599. uint enh_start; /* in 512-byte sectors */
  600. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  601. unsigned wr_rel_change : 1;
  602. unsigned wr_rel_set : 1;
  603. } user;
  604. struct {
  605. uint size; /* in 512-byte sectors */
  606. unsigned enhanced : 1;
  607. unsigned wr_rel_change : 1;
  608. unsigned wr_rel_set : 1;
  609. } gp_part[4];
  610. };
  611. enum mmc_hwpart_conf_mode {
  612. MMC_HWPART_CONF_CHECK,
  613. MMC_HWPART_CONF_SET,
  614. MMC_HWPART_CONF_COMPLETE,
  615. };
  616. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  617. /**
  618. * mmc_bind() - Set up a new MMC device ready for probing
  619. *
  620. * A child block device is bound with the IF_TYPE_MMC interface type. This
  621. * allows the device to be used with CONFIG_BLK
  622. *
  623. * @dev: MMC device to set up
  624. * @mmc: MMC struct
  625. * @cfg: MMC configuration
  626. * @return 0 if OK, -ve on error
  627. */
  628. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  629. const struct mmc_config *cfg);
  630. void mmc_destroy(struct mmc *mmc);
  631. /**
  632. * mmc_unbind() - Unbind a MMC device's child block device
  633. *
  634. * @dev: MMC device
  635. * @return 0 if OK, -ve on error
  636. */
  637. int mmc_unbind(struct udevice *dev);
  638. int mmc_initialize(struct bd_info *bis);
  639. int mmc_init_device(int num);
  640. int mmc_init(struct mmc *mmc);
  641. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  642. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  643. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  644. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  645. int mmc_deinit(struct mmc *mmc);
  646. #endif
  647. /**
  648. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  649. *
  650. * @dev: MMC device
  651. * @cfg: MMC configuration
  652. * @return 0 if OK, -ve on error
  653. */
  654. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  655. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  656. /**
  657. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  658. *
  659. * @voltage: The mmc_voltage to convert
  660. * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  661. */
  662. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  663. /**
  664. * mmc_set_clock() - change the bus clock
  665. * @mmc: MMC struct
  666. * @clock: bus frequency in Hz
  667. * @disable: flag indicating if the clock must on or off
  668. * @return 0 if OK, -ve on error
  669. */
  670. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  671. #define MMC_CLK_ENABLE false
  672. #define MMC_CLK_DISABLE true
  673. struct mmc *find_mmc_device(int dev_num);
  674. int mmc_set_dev(int dev_num);
  675. void print_mmc_devices(char separator);
  676. /**
  677. * get_mmc_num() - get the total MMC device number
  678. *
  679. * @return 0 if there is no MMC device, else the number of devices
  680. */
  681. int get_mmc_num(void);
  682. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  683. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  684. enum mmc_hwpart_conf_mode mode);
  685. #if !CONFIG_IS_ENABLED(DM_MMC)
  686. int mmc_getcd(struct mmc *mmc);
  687. int board_mmc_getcd(struct mmc *mmc);
  688. int mmc_getwp(struct mmc *mmc);
  689. int board_mmc_getwp(struct mmc *mmc);
  690. #endif
  691. int mmc_set_dsr(struct mmc *mmc, u16 val);
  692. /* Function to change the size of boot partition and rpmb partitions */
  693. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  694. unsigned long rpmbsize);
  695. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  696. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  697. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  698. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  699. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  700. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  701. /* Functions to read / write the RPMB partition */
  702. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  703. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  704. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  705. unsigned short cnt, unsigned char *key);
  706. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  707. unsigned short cnt, unsigned char *key);
  708. /**
  709. * mmc_rpmb_route_frames() - route RPMB data frames
  710. * @mmc Pointer to a MMC device struct
  711. * @req Request data frames
  712. * @reqlen Length of data frames in bytes
  713. * @rsp Supplied buffer for response data frames
  714. * @rsplen Length of supplied buffer for response data frames
  715. *
  716. * The RPMB data frames are routed to/from some external entity, for
  717. * example a Trusted Exectuion Environment in an arm TrustZone protected
  718. * secure world. It's expected that it's the external entity who is in
  719. * control of the RPMB key.
  720. *
  721. * Returns 0 on success, < 0 on error.
  722. */
  723. int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
  724. void *rsp, unsigned long rsplen);
  725. #ifdef CONFIG_CMD_BKOPS_ENABLE
  726. int mmc_set_bkops_enable(struct mmc *mmc);
  727. #endif
  728. /**
  729. * Start device initialization and return immediately; it does not block on
  730. * polling OCR (operation condition register) status. Useful for checking
  731. * the presence of SD/eMMC when no card detect logic is available.
  732. *
  733. * @param mmc Pointer to a MMC device struct
  734. * @return 0 on success, <0 on error.
  735. */
  736. int mmc_get_op_cond(struct mmc *mmc);
  737. /**
  738. * Start device initialization and return immediately; it does not block on
  739. * polling OCR (operation condition register) status. Then you should call
  740. * mmc_init, which would block on polling OCR status and complete the device
  741. * initializatin.
  742. *
  743. * @param mmc Pointer to a MMC device struct
  744. * @return 0 on success, <0 on error.
  745. */
  746. int mmc_start_init(struct mmc *mmc);
  747. /**
  748. * Set preinit flag of mmc device.
  749. *
  750. * This will cause the device to be pre-inited during mmc_initialize(),
  751. * which may save boot time if the device is not accessed until later.
  752. * Some eMMC devices take 200-300ms to init, but unfortunately they
  753. * must be sent a series of commands to even get them to start preparing
  754. * for operation.
  755. *
  756. * @param mmc Pointer to a MMC device struct
  757. * @param preinit preinit flag value
  758. */
  759. void mmc_set_preinit(struct mmc *mmc, int preinit);
  760. #ifdef CONFIG_MMC_SPI
  761. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  762. #else
  763. #define mmc_host_is_spi(mmc) 0
  764. #endif
  765. void board_mmc_power_init(void);
  766. int board_mmc_init(struct bd_info *bis);
  767. int cpu_mmc_init(struct bd_info *bis);
  768. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  769. # ifdef CONFIG_SYS_MMC_ENV_PART
  770. extern uint mmc_get_env_part(struct mmc *mmc);
  771. # endif
  772. int mmc_get_env_dev(void);
  773. /* Minimum partition switch timeout in units of 10-milliseconds */
  774. #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
  775. /* Set block count limit because of 16 bit register limit on some hardware*/
  776. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  777. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
  778. #endif
  779. /**
  780. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  781. *
  782. * @mmc: MMC device
  783. * @return block device if found, else NULL
  784. */
  785. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  786. static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
  787. {
  788. return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  789. }
  790. #endif /* _MMC_H_ */