starfive_devkits.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <asm/gpio.h>
  11. #include <cpu_func.h>
  12. #include <dm/uclass.h>
  13. #include <dm/device.h>
  14. #include <env.h>
  15. #include <i2c.h>
  16. #include <inttypes.h>
  17. #include <misc.h>
  18. #include <linux/bitops.h>
  19. #include <asm/arch/gpio.h>
  20. #include <bmp_logo.h>
  21. #include <video.h>
  22. #include <splash.h>
  23. #include <asm/gpio.h>
  24. #include <linux/err.h>
  25. #define SYS_CLOCK_ENABLE(clk) \
  26. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  27. #define CPU_VOL_BINNING_OFFSET 0x7fc
  28. enum {
  29. BOOT_FLASH = 0,
  30. BOOT_SD,
  31. BOOT_EMMC,
  32. BOOT_UART,
  33. };
  34. enum cpu_voltage_type_t {
  35. CPU_VOL_1020 = 0xef0,
  36. CPU_VOL_1040 = 0xfff,
  37. CPU_VOL_1060 = 0xff0,
  38. CPU_VOL_1000 = 0x8f0,
  39. };
  40. #define CPU_VOL_MASK 0xfff
  41. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  42. {
  43. u32 value;
  44. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  45. do {
  46. value = in_le32(SYS_CRG_BASE + status);
  47. } while ((value & BIT(rst)) != BIT(rst));
  48. }
  49. static void jh7110_timer_init(void)
  50. {
  51. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  52. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  53. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  54. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  55. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  56. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  57. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  58. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  59. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  60. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  61. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  62. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  63. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  64. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  65. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  66. }
  67. static void jh7110_i2c_init (int id)
  68. {
  69. switch (id) {
  70. case 5:
  71. //scl
  72. SYS_IOMUX_COMPLEX(19, 79, 0, 42);
  73. //sda
  74. SYS_IOMUX_COMPLEX(20, 80, 0, 43);
  75. break;
  76. default:
  77. break;
  78. }
  79. }
  80. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  81. {
  82. switch (id) {
  83. case 0:
  84. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  85. GMAC5_0_CLK_TX_MASK,
  86. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  87. break;
  88. case 1:
  89. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  90. GMAC5_1_CLK_TX_MASK,
  91. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  92. break;
  93. default:
  94. break;
  95. }
  96. }
  97. static void jh7110_gmac_io_pad(int id)
  98. {
  99. u32 cap = BIT(0); /* 2.5V */
  100. switch (id) {
  101. case 0:
  102. /* Improved GMAC0 TX I/O PAD capability */
  103. clrsetbits_le32(AON_IOMUX_BASE + 0x78, 0x3, cap & 0x3);
  104. clrsetbits_le32(AON_IOMUX_BASE + 0x7c, 0x3, cap & 0x3);
  105. clrsetbits_le32(AON_IOMUX_BASE + 0x80, 0x3, cap & 0x3);
  106. clrsetbits_le32(AON_IOMUX_BASE + 0x84, 0x3, cap & 0x3);
  107. clrsetbits_le32(AON_IOMUX_BASE + 0x88, 0x3, cap & 0x3);
  108. break;
  109. case 1:
  110. /* Improved GMAC1 TX I/O PAD capability */
  111. clrsetbits_le32(SYS_IOMUX_BASE + 0x26c, 0x3, cap & 0x3);
  112. clrsetbits_le32(SYS_IOMUX_BASE + 0x270, 0x3, cap & 0x3);
  113. clrsetbits_le32(SYS_IOMUX_BASE + 0x274, 0x3, cap & 0x3);
  114. clrsetbits_le32(SYS_IOMUX_BASE + 0x278, 0x3, cap & 0x3);
  115. clrsetbits_le32(SYS_IOMUX_BASE + 0x27c, 0x3, cap & 0x3);
  116. break;
  117. }
  118. }
  119. static void jh7110_gmac_init(int id)
  120. {
  121. jh7110_gmac_sel_tx_to_rgmii(id);
  122. jh7110_gmac_io_pad(id);
  123. }
  124. static void jh7110_usb_init(bool usb2_enable)
  125. {
  126. if (usb2_enable) {
  127. /*usb 2.0 utmi phy init*/
  128. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  129. USB_MODE_STRAP_MASK,
  130. (2<<USB_MODE_STRAP_SHIFT) &
  131. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  132. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  133. USB_OTG_SUSPENDM_BYPS_MASK,
  134. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  135. & USB_OTG_SUSPENDM_BYPS_MASK);
  136. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  137. USB_OTG_SUSPENDM_MASK,
  138. BIT(USB_OTG_SUSPENDM_SHIFT) &
  139. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  140. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  141. USB_PLL_EN_MASK,
  142. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  143. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  144. USB_REFCLK_MODE_MASK,
  145. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  146. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  147. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  148. PDRSTN_SPLIT_MASK,
  149. BIT(PDRSTN_SPLIT_SHIFT) &
  150. PDRSTN_SPLIT_MASK);
  151. } else {
  152. /*usb 3.0 pipe phy config*/
  153. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  154. PCIE_CKREF_SRC_MASK,
  155. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  156. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  157. PCIE_CLK_SEL_MASK,
  158. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  159. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  160. PCIE_PHY_MODE_MASK,
  161. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  162. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  163. PCIE_USB3_BUS_WIDTH_MASK,
  164. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  165. PCIE_USB3_BUS_WIDTH_MASK);
  166. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  167. PCIE_USB3_RATE_MASK,
  168. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  169. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  170. PCIE_USB3_RX_STANDBY_MASK,
  171. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  172. & PCIE_USB3_RX_STANDBY_MASK);
  173. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  174. PCIE_USB3_PHY_ENABLE_MASK,
  175. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  176. & PCIE_USB3_PHY_ENABLE_MASK);
  177. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  178. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  179. PDRSTN_SPLIT_MASK,
  180. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  181. }
  182. }
  183. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  184. static void get_cpu_voltage_type(struct udevice *dev)
  185. {
  186. int ret;
  187. u32 buf = CPU_VOL_1040;
  188. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  189. if (ret != sizeof(buf))
  190. printf("%s: error reading CPU vol from OTP\n", __func__);
  191. else {
  192. switch ((buf & CPU_VOL_MASK)) {
  193. case CPU_VOL_1000:
  194. env_set("cpu_max_vol", "1000000");
  195. break;
  196. case CPU_VOL_1060:
  197. env_set("cpu_max_vol", "1060000");
  198. break;
  199. case CPU_VOL_1020:
  200. env_set("cpu_max_vol", "1020000");
  201. break;
  202. default:
  203. break;
  204. }
  205. }
  206. }
  207. #endif
  208. static void get_boot_mode(void)
  209. {
  210. u32 value;
  211. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  212. switch (value & 0x03) {
  213. case BOOT_FLASH:
  214. env_set("bootmode", "flash");
  215. env_set("devnum", "1");
  216. break;
  217. case BOOT_SD:
  218. env_set("bootmode", "sd");
  219. env_set("devnum", "1");
  220. break;
  221. case BOOT_EMMC:
  222. env_set("bootmode", "emmc");
  223. env_set("devnum", "0");
  224. break;
  225. default:
  226. env_set("bootmode", "uart");
  227. env_set("devnum", "1");
  228. break;
  229. }
  230. }
  231. #define CONFIG_SYS_PMIC_BUS_NUM 5
  232. #define CONFIG_SYS_I2C_PMIC_ADDR 0x36
  233. #define CONFIG_SYS_I2C_PMIC_ADDR_LEN 1
  234. #define AXP15060_DCDC_MODE_CTRL_2 0x1b
  235. #define AXP15060_DCDC5_MODE_BIT BIT(4)
  236. #define AXP15060_PWR_SEQUENCE_CTRL 0X32
  237. #define AXP15060_RST_PMIC_BY_PWROK_BIT BIT(4)
  238. int set_pmic(void)
  239. {
  240. int ret;
  241. struct udevice *dev;
  242. u8 temp_buf;
  243. ret = i2c_get_chip_for_busnum(CONFIG_SYS_PMIC_BUS_NUM,
  244. CONFIG_SYS_I2C_PMIC_ADDR,
  245. CONFIG_SYS_I2C_PMIC_ADDR_LEN,
  246. &dev);
  247. if (!ret) {
  248. /* Set Pmic DCDC5 Mode as PWM */
  249. ret = dm_i2c_read(dev,
  250. AXP15060_DCDC_MODE_CTRL_2,
  251. &temp_buf,
  252. sizeof(temp_buf));
  253. if (ret)
  254. printf("%s: can't read pmic dcdc5 mode register\n",
  255. __func__);
  256. temp_buf = temp_buf | AXP15060_DCDC5_MODE_BIT;
  257. ret = dm_i2c_write(dev,
  258. AXP15060_DCDC_MODE_CTRL_2,
  259. &temp_buf,
  260. sizeof(temp_buf));
  261. if (ret)
  262. printf("%s: can't write pmic dcdc5 mode register\n",
  263. __func__);
  264. /* Enable PWROK in PMIC */
  265. ret = dm_i2c_read(dev,
  266. AXP15060_PWR_SEQUENCE_CTRL,
  267. &temp_buf,
  268. sizeof(temp_buf));
  269. if (ret)
  270. printf("%s: can't read pmic power disbale & down sequence register\n",
  271. __func__);
  272. temp_buf = temp_buf | AXP15060_RST_PMIC_BY_PWROK_BIT;
  273. ret = dm_i2c_write(dev,
  274. AXP15060_PWR_SEQUENCE_CTRL,
  275. &temp_buf,
  276. sizeof(temp_buf));
  277. if (ret)
  278. printf("%s: can't write pmic power disbale & down sequence register\n",
  279. __func__);
  280. }
  281. return 0;
  282. }
  283. int board_init(void)
  284. {
  285. enable_caches();
  286. jh7110_timer_init();
  287. jh7110_usb_init(true);
  288. jh7110_gmac_init(0);
  289. jh7110_gmac_init(1);
  290. jh7110_i2c_init(5);
  291. return 0;
  292. }
  293. #ifdef CONFIG_MISC_INIT_R
  294. int misc_init_r(void)
  295. {
  296. char mac0[6] = {0x6c, 0xcf, 0x39, 0x6c, 0xde, 0xad};
  297. char mac1[6] = {0x6c, 0xcf, 0x39, 0x7c, 0xae, 0x5d};
  298. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  299. struct udevice *dev;
  300. char buf[16];
  301. int ret;
  302. #define MACADDR_OFFSET 0x8
  303. ret = uclass_get_device_by_driver(UCLASS_MISC,
  304. DM_DRIVER_GET(starfive_otp), &dev);
  305. if (ret) {
  306. debug("%s: could not find otp device\n", __func__);
  307. goto err;
  308. }
  309. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  310. if (ret != sizeof(buf))
  311. printf("%s: error reading mac from OTP\n", __func__);
  312. else
  313. if (buf[0] != 0xff) {
  314. memcpy(mac0, buf, 6);
  315. memcpy(mac1, &buf[8], 6);
  316. }
  317. err:
  318. #endif
  319. eth_env_set_enetaddr("eth0addr", mac0);
  320. eth_env_set_enetaddr("eth1addr", mac1);
  321. /* Set the default cpu max voltage. */
  322. env_set("cpu_max_vol", "1040000");
  323. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  324. get_cpu_voltage_type(dev);
  325. #endif
  326. return 0;
  327. }
  328. #endif
  329. int board_late_init(void)
  330. {
  331. struct udevice *dev;
  332. int ret;
  333. get_boot_mode();
  334. env_set("chip_vision", "B");
  335. /*
  336. * save the memory info by environment variable in u-boot,
  337. * It will used to update the memory configuration in dts,
  338. * which passed to kernel lately.
  339. */
  340. env_set_hex("memory_addr", gd->ram_base);
  341. env_set_hex("memory_size", gd->ram_size);
  342. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  343. if (ret)
  344. return ret;
  345. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  346. if (ret)
  347. goto err;
  348. err:
  349. return 0;
  350. }
  351. static int jh7110_get_gpio_val(u32 gpio)
  352. {
  353. int ret;
  354. ret = gpio_request(gpio, "ddr_gpio");
  355. if (!ret) {
  356. ret = gpio_direction_input(gpio);
  357. if (!ret)
  358. ret = gpio_get_value(gpio);
  359. gpio_free(gpio);
  360. }
  361. return ret;
  362. }
  363. int board_ddr_size(void)
  364. {
  365. int val, ret;
  366. val = jh7110_get_gpio_val(21);
  367. if (IS_ERR_VALUE(val))
  368. return val;
  369. ret = jh7110_get_gpio_val(22);
  370. if (IS_ERR_VALUE(ret))
  371. return ret;
  372. val |= (ret << 1);
  373. switch (val) {
  374. case 0x0:
  375. ret = 8; //8GB
  376. break;
  377. case 0x1:
  378. ret = 4; //4GB
  379. break;
  380. case 0x2:
  381. ret = 2; //2GB
  382. break;
  383. case 0x3:
  384. ret = 1; //1GB
  385. break;
  386. default:
  387. ret = -EINVAL;
  388. break;
  389. };
  390. return ret;
  391. }
  392. static int starfive_get_gpio_val(u32 gpio)
  393. {
  394. int ret;
  395. ret = gpio_request(gpio, "ddr_gpio");
  396. if (!ret) {
  397. ret = gpio_direction_input(gpio);
  398. if (!ret)
  399. ret = gpio_get_value(gpio);
  400. gpio_free(gpio);
  401. }
  402. return ret;
  403. }
  404. /* get ddr type from GPIO23,GPIO24 DDR4 or LPDDR4 */
  405. int starfive_get_ddr_type(void)
  406. {
  407. int val, ret;
  408. val = starfive_get_gpio_val(23);
  409. if (IS_ERR_VALUE(val))
  410. return val;
  411. ret = starfive_get_gpio_val(24);
  412. if (IS_ERR_VALUE(ret))
  413. return ret;
  414. return val | (ret << 1);
  415. }