walnut405.c 4.2 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include "walnut405.h"
  25. #include <asm/processor.h>
  26. #include <spd_sdram.h>
  27. int board_early_init_f (void)
  28. {
  29. /*-------------------------------------------------------------------------+
  30. | Interrupt controller setup for the Walnut board.
  31. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  32. | IRQ 16 405GP internally generated; active low; level sensitive
  33. | IRQ 17-24 RESERVED
  34. | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  35. | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  36. | IRQ 27 (EXT IRQ 2) Not Used
  37. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  38. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  39. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  40. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  41. | Note for Walnut board:
  42. | An interrupt taken for the FPGA (IRQ 25) indicates that either
  43. | the Mouse, Keyboard, IRDA, or External Expansion caused the
  44. | interrupt. The FPGA must be read to determine which device
  45. | caused the interrupt. The default setting of the FPGA clears
  46. |
  47. +-------------------------------------------------------------------------*/
  48. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  49. mtdcr (uicer, 0x00000000); /* disable all ints */
  50. mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
  51. mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
  52. mtdcr (uictr, 0x10000000); /* set int trigger levels */
  53. mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  54. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  55. #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
  56. /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
  57. mtebc (pb1ap, 0x02815480);
  58. mtebc (pb1cr, 0xF0018000);
  59. /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  60. mtebc (pb2ap, 0x04815A80);
  61. mtebc (pb2cr, 0xF0118000);
  62. /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
  63. mtebc (pb3ap, 0x01815280);
  64. mtebc (pb3cr, 0xF0218000);
  65. /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  66. mtebc (pb7ap, 0x01815280);
  67. mtebc (pb7cr, 0xF0318000);
  68. /* set UART1 control to select CTS/RTS */
  69. #define FPGA_BRDC 0xF0300004
  70. *(volatile char *) (FPGA_BRDC) |= 0x1;
  71. return 0;
  72. }
  73. /* ------------------------------------------------------------------------- */
  74. /*
  75. * Check Board Identity:
  76. */
  77. int checkboard (void)
  78. {
  79. unsigned char *s = getenv ("serial#");
  80. unsigned char *e;
  81. puts ("Board: ");
  82. if (!s || strncmp (s, "WALNUT405", 9)) {
  83. puts ("### No HW ID - assuming WALNUT405");
  84. } else {
  85. for (e = s; *e; ++e) {
  86. if (*e == ' ')
  87. break;
  88. }
  89. for (; s < e; ++s) {
  90. putc (*s);
  91. }
  92. }
  93. putc ('\n');
  94. return (0);
  95. }
  96. /* -------------------------------------------------------------------------
  97. initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  98. the necessary info for SDRAM controller configuration
  99. ------------------------------------------------------------------------- */
  100. long int initdram (int board_type)
  101. {
  102. return spd_sdram (0);
  103. }
  104. /* ------------------------------------------------------------------------- */
  105. int testdram (void)
  106. {
  107. /* TODO: XXX XXX XXX */
  108. printf ("test: xxx MB - ok\n");
  109. return (0);
  110. }
  111. /* ------------------------------------------------------------------------- */