init.S 4.1 KB

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  1. /*------------------------------------------------------------------------------+ */
  2. /* */
  3. /* This source code has been made available to you by IBM on an AS-IS */
  4. /* basis. Anyone receiving this source is licensed under IBM */
  5. /* copyrights to use it in any way he or she deems fit, including */
  6. /* copying it, modifying it, compiling it, and redistributing it either */
  7. /* with or without modifications. No license under IBM patents or */
  8. /* patent applications is to be implied by the copyright license. */
  9. /* */
  10. /* Any user of this software should understand that IBM cannot provide */
  11. /* technical support for this software and will not be responsible for */
  12. /* any consequences resulting from the use of this software. */
  13. /* */
  14. /* Any person who transfers this source code or any derivative work */
  15. /* must include the IBM copyright notice, this paragraph, and the */
  16. /* preceding two paragraphs in the transferred software. */
  17. /* */
  18. /* COPYRIGHT I B M CORPORATION 1995 */
  19. /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
  20. /*------------------------------------------------------------------------------- */
  21. /*----------------------------------------------------------------------------- */
  22. /* Function: ext_bus_cntlr_init */
  23. /* Description: Initializes the External Bus Controller for the external */
  24. /* peripherals. IMPORTANT: For pass1 this code must run from */
  25. /* cache since you can not reliably change a peripheral banks */
  26. /* timing register (pbxap) while running code from that bank. */
  27. /* For ex., since we are running from ROM on bank 0, we can NOT */
  28. /* execute the code that modifies bank 0 timings from ROM, so */
  29. /* we run it from cache. */
  30. /* Bank 0 - Flash and SRAM */
  31. /* Bank 1 - NVRAM/RTC */
  32. /* Bank 2 - Keyboard/Mouse controller */
  33. /* Bank 3 - IR controller */
  34. /* Bank 4 - not used */
  35. /* Bank 5 - not used */
  36. /* Bank 6 - not used */
  37. /* Bank 7 - FPGA registers */
  38. /*----------------------------------------------------------------------------- */
  39. #include <ppc4xx.h>
  40. #include <ppc_asm.tmpl>
  41. #include <ppc_defs.h>
  42. #include <asm/cache.h>
  43. #include <asm/mmu.h>
  44. .globl ext_bus_cntlr_init
  45. ext_bus_cntlr_init:
  46. mflr r4 /* save link register */
  47. bl ..getAddr
  48. ..getAddr:
  49. mflr r3 /* get address of ..getAddr */
  50. mtlr r4 /* restore link register */
  51. addi r4,0,14 /* set ctr to 10; used to prefetch */
  52. mtctr r4 /* 10 cache lines to fit this function */
  53. /* in cache (gives us 8x10=80 instrctns) */
  54. ..ebcloop:
  55. icbt r0,r3 /* prefetch cache line for addr in r3 */
  56. addi r3,r3,32 /* move to next cache line */
  57. bdnz ..ebcloop /* continue for 10 cache lines */
  58. /*------------------------------------------------------------------- */
  59. /* Delay to ensure all accesses to ROM are complete before changing */
  60. /* bank 0 timings. 200usec should be enough. */
  61. /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
  62. /*------------------------------------------------------------------- */
  63. addis r3,0,0x0
  64. ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  65. mtctr r3
  66. ..spinlp:
  67. bdnz ..spinlp /* spin loop */
  68. /*----------------------------------------------------------------------- */
  69. /* Memory Bank 0 (Flash and SRAM) initialization */
  70. /*----------------------------------------------------------------------- */
  71. addi r4,0,pb0ap
  72. mtdcr ebccfga,r4
  73. addis r4,0,0x9B01
  74. ori r4,r4,0x5480
  75. mtdcr ebccfgd,r4
  76. addi r4,0,pb0cr
  77. mtdcr ebccfga,r4
  78. addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
  79. ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
  80. mtdcr ebccfgd,r4
  81. blr
  82. /*----------------------------------------------------------------------------- */
  83. /* Function: sdram_init */
  84. /* Description: Dummy implementation here - done in C later */
  85. /*----------------------------------------------------------------------------- */
  86. .globl sdram_init
  87. sdram_init:
  88. blr