bubinga405ep.c 2.9 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. long int spd_sdram (void);
  24. #include <common.h>
  25. #include <asm/processor.h>
  26. int board_early_init_f (void)
  27. {
  28. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  29. mtdcr (uicer, 0x00000000); /* disable all ints */
  30. mtdcr (uiccr, 0x00000010);
  31. mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
  32. mtdcr (uictr, 0x00000010); /* set int trigger levels */
  33. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  34. #if 0
  35. #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
  36. /* CS1 */
  37. /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
  38. mtebc (pb1ap, 0x02815480);
  39. mtebc (pb1cr, 0xF0018000);
  40. p = (unsigned int*)0xEF600708;
  41. t = *p;
  42. t = t | 0x00000400;
  43. *p = t;
  44. /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  45. mtebc (pb2ap, 0x04815A80);
  46. mtebc (pb2cr, 0xF0118000);
  47. /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
  48. mtebc (pb3ap, 0x01815280);
  49. mtebc (pb3cr, 0xF0218000);
  50. /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  51. mtebc (pb7ap, 0x01815280);
  52. mtebc (pb7cr, 0xF0318000);
  53. /* set UART1 control to select CTS/RTS */
  54. #define FPGA_BRDC 0xF0300004
  55. *(volatile char *) (FPGA_BRDC) |= 0x1;
  56. #endif
  57. return 0;
  58. }
  59. /* ------------------------------------------------------------------------- */
  60. /*
  61. * Check Board Identity:
  62. */
  63. int checkboard (void)
  64. {
  65. unsigned char *s = getenv ("serial#");
  66. puts ("Board: IBM 405EP Eval Board");
  67. if (s != NULL) {
  68. puts (", serial# ");
  69. puts (s);
  70. }
  71. putc ('\n');
  72. return (0);
  73. }
  74. /* -------------------------------------------------------------------------
  75. initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  76. the necessary info for SDRAM controller configuration
  77. ------------------------------------------------------------------------- */
  78. long int initdram (int board_type)
  79. {
  80. long int ret;
  81. ret = spd_sdram ();
  82. return ret;
  83. }
  84. /* ------------------------------------------------------------------------- */
  85. int testdram (void)
  86. {
  87. /* TODO: XXX XXX XXX */
  88. printf ("test: xxx MB - ok\n");
  89. return (0);
  90. }
  91. /* ------------------------------------------------------------------------- */