tpm-v2.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. struct udevice;
  17. #define TPM2_DIGEST_LEN 32
  18. #define TPM2_SHA1_DIGEST_SIZE 20
  19. #define TPM2_SHA256_DIGEST_SIZE 32
  20. #define TPM2_SHA384_DIGEST_SIZE 48
  21. #define TPM2_SHA512_DIGEST_SIZE 64
  22. #define TPM2_SM3_256_DIGEST_SIZE 32
  23. #define TPM2_MAX_PCRS 32
  24. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  25. #define TPM2_MAX_CAP_BUFFER 1024
  26. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  27. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  28. /*
  29. * We deviate from this draft of the specification by increasing the value of
  30. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  31. * implementations that have enabled a larger than typical number of PCR
  32. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  33. * in a future revision of the specification.
  34. */
  35. #define TPM2_NUM_PCR_BANKS 16
  36. /* Definition of (UINT32) TPM2_CAP Constants */
  37. #define TPM2_CAP_PCRS 0x00000005U
  38. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  39. /* Definition of (UINT32) TPM2_PT Constants */
  40. #define TPM2_PT_GROUP (u32)(0x00000100)
  41. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  42. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  43. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  44. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  45. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  46. /*
  47. * event types, cf.
  48. * "TCG Server Management Domain Firmware Profile Specification",
  49. * rev 1.00, 2020-05-01
  50. */
  51. #define EV_POST_CODE ((u32)0x00000001)
  52. #define EV_NO_ACTION ((u32)0x00000003)
  53. #define EV_SEPARATOR ((u32)0x00000004)
  54. #define EV_ACTION ((u32)0x00000005)
  55. #define EV_TAG ((u32)0x00000006)
  56. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  57. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  58. #define EV_CPU_MICROCODE ((u32)0x00000009)
  59. #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
  60. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  61. #define EV_COMPACT_HASH ((u32)0x0000000C)
  62. /* TPMS_TAGGED_PROPERTY Structure */
  63. struct tpms_tagged_property {
  64. u32 property;
  65. u32 value;
  66. } __packed;
  67. /* TPMS_PCR_SELECTION Structure */
  68. struct tpms_pcr_selection {
  69. u16 hash;
  70. u8 size_of_select;
  71. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  72. } __packed;
  73. /* TPML_PCR_SELECTION Structure */
  74. struct tpml_pcr_selection {
  75. u32 count;
  76. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  77. } __packed;
  78. /* TPML_TAGGED_TPM_PROPERTY Structure */
  79. struct tpml_tagged_tpm_property {
  80. u32 count;
  81. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  82. } __packed;
  83. /* TPMU_CAPABILITIES Union */
  84. union tpmu_capabilities {
  85. /*
  86. * Non exhaustive. Only added the structs needed for our
  87. * current code
  88. */
  89. struct tpml_pcr_selection assigned_pcr;
  90. struct tpml_tagged_tpm_property tpm_properties;
  91. } __packed;
  92. /* TPMS_CAPABILITY_DATA Structure */
  93. struct tpms_capability_data {
  94. u32 capability;
  95. union tpmu_capabilities data;
  96. } __packed;
  97. /**
  98. * SHA1 Event Log Entry Format
  99. *
  100. * @pcr_index: PCRIndex event extended to
  101. * @event_type: Type of event (see EFI specs)
  102. * @digest: Value extended into PCR index
  103. * @event_size: Size of event
  104. * @event: Event data
  105. */
  106. struct tcg_pcr_event {
  107. u32 pcr_index;
  108. u32 event_type;
  109. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  110. u32 event_size;
  111. u8 event[];
  112. } __packed;
  113. /**
  114. * Definition of TPMU_HA Union
  115. */
  116. union tmpu_ha {
  117. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  118. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  119. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  120. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  121. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  122. } __packed;
  123. /**
  124. * Definition of TPMT_HA Structure
  125. *
  126. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  127. * @digest: Digest value for a given algorithm
  128. */
  129. struct tpmt_ha {
  130. u16 hash_alg;
  131. union tmpu_ha digest;
  132. } __packed;
  133. /**
  134. * Definition of TPML_DIGEST_VALUES Structure
  135. *
  136. * @count: Number of algorithms supported by hardware
  137. * @digests: struct for algorithm id and hash value
  138. */
  139. struct tpml_digest_values {
  140. u32 count;
  141. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  142. } __packed;
  143. /**
  144. * Crypto Agile Log Entry Format
  145. *
  146. * @pcr_index: PCRIndex event extended to
  147. * @event_type: Type of event
  148. * @digests: List of digestsextended to PCR index
  149. * @event_size: Size of the event data
  150. * @event: Event data
  151. */
  152. struct tcg_pcr_event2 {
  153. u32 pcr_index;
  154. u32 event_type;
  155. struct tpml_digest_values digests;
  156. u32 event_size;
  157. u8 event[];
  158. } __packed;
  159. /**
  160. * TPM2 Structure Tags for command/response buffers.
  161. *
  162. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  163. * @TPM2_ST_SESSIONS: the command needs an authentication.
  164. */
  165. enum tpm2_structures {
  166. TPM2_ST_NO_SESSIONS = 0x8001,
  167. TPM2_ST_SESSIONS = 0x8002,
  168. };
  169. /**
  170. * TPM2 type of boolean.
  171. */
  172. enum tpm2_yes_no {
  173. TPMI_YES = 1,
  174. TPMI_NO = 0,
  175. };
  176. /**
  177. * TPM2 startup values.
  178. *
  179. * @TPM2_SU_CLEAR: reset the internal state.
  180. * @TPM2_SU_STATE: restore saved state (if any).
  181. */
  182. enum tpm2_startup_types {
  183. TPM2_SU_CLEAR = 0x0000,
  184. TPM2_SU_STATE = 0x0001,
  185. };
  186. /**
  187. * TPM2 permanent handles.
  188. *
  189. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  190. * @TPM2_RS_PW: indicates a password.
  191. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  192. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  193. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  194. */
  195. enum tpm2_handles {
  196. TPM2_RH_OWNER = 0x40000001,
  197. TPM2_RS_PW = 0x40000009,
  198. TPM2_RH_LOCKOUT = 0x4000000A,
  199. TPM2_RH_ENDORSEMENT = 0x4000000B,
  200. TPM2_RH_PLATFORM = 0x4000000C,
  201. };
  202. /**
  203. * TPM2 command codes used at the beginning of a buffer, gives the command.
  204. *
  205. * @TPM2_CC_STARTUP: TPM2_Startup().
  206. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  207. * @TPM2_CC_CLEAR: TPM2_Clear().
  208. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  209. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  210. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  211. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  212. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  213. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  214. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  215. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  216. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  217. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  218. */
  219. enum tpm2_command_codes {
  220. TPM2_CC_STARTUP = 0x0144,
  221. TPM2_CC_SELF_TEST = 0x0143,
  222. TPM2_CC_HIER_CONTROL = 0x0121,
  223. TPM2_CC_CLEAR = 0x0126,
  224. TPM2_CC_CLEARCONTROL = 0x0127,
  225. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  226. TPM2_CC_NV_DEFINE_SPACE = 0x012a,
  227. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  228. TPM2_CC_NV_WRITE = 0x0137,
  229. TPM2_CC_NV_WRITELOCK = 0x0138,
  230. TPM2_CC_DAM_RESET = 0x0139,
  231. TPM2_CC_DAM_PARAMETERS = 0x013A,
  232. TPM2_CC_NV_READ = 0x014E,
  233. TPM2_CC_GET_CAPABILITY = 0x017A,
  234. TPM2_CC_GET_RANDOM = 0x017B,
  235. TPM2_CC_PCR_READ = 0x017E,
  236. TPM2_CC_PCR_EXTEND = 0x0182,
  237. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  238. };
  239. /**
  240. * TPM2 return codes.
  241. */
  242. enum tpm2_return_codes {
  243. TPM2_RC_SUCCESS = 0x0000,
  244. TPM2_RC_BAD_TAG = 0x001E,
  245. TPM2_RC_FMT1 = 0x0080,
  246. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  247. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  248. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  249. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  250. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  251. TPM2_RC_VER1 = 0x0100,
  252. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  253. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  254. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  255. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  256. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  257. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  258. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  259. TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
  260. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  261. TPM2_RC_WARN = 0x0900,
  262. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  263. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  264. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  265. };
  266. /**
  267. * TPM2 algorithms.
  268. */
  269. enum tpm2_algorithms {
  270. TPM2_ALG_SHA1 = 0x04,
  271. TPM2_ALG_XOR = 0x0A,
  272. TPM2_ALG_SHA256 = 0x0B,
  273. TPM2_ALG_SHA384 = 0x0C,
  274. TPM2_ALG_SHA512 = 0x0D,
  275. TPM2_ALG_NULL = 0x10,
  276. TPM2_ALG_SM3_256 = 0x12,
  277. };
  278. /* NV index attributes */
  279. enum tpm_index_attrs {
  280. TPMA_NV_PPWRITE = 1UL << 0,
  281. TPMA_NV_OWNERWRITE = 1UL << 1,
  282. TPMA_NV_AUTHWRITE = 1UL << 2,
  283. TPMA_NV_POLICYWRITE = 1UL << 3,
  284. TPMA_NV_COUNTER = 1UL << 4,
  285. TPMA_NV_BITS = 1UL << 5,
  286. TPMA_NV_EXTEND = 1UL << 6,
  287. TPMA_NV_POLICY_DELETE = 1UL << 10,
  288. TPMA_NV_WRITELOCKED = 1UL << 11,
  289. TPMA_NV_WRITEALL = 1UL << 12,
  290. TPMA_NV_WRITEDEFINE = 1UL << 13,
  291. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  292. TPMA_NV_GLOBALLOCK = 1UL << 15,
  293. TPMA_NV_PPREAD = 1UL << 16,
  294. TPMA_NV_OWNERREAD = 1UL << 17,
  295. TPMA_NV_AUTHREAD = 1UL << 18,
  296. TPMA_NV_POLICYREAD = 1UL << 19,
  297. TPMA_NV_NO_DA = 1UL << 25,
  298. TPMA_NV_ORDERLY = 1UL << 26,
  299. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  300. TPMA_NV_READLOCKED = 1UL << 28,
  301. TPMA_NV_WRITTEN = 1UL << 29,
  302. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  303. TPMA_NV_READ_STCLEAR = 1UL << 31,
  304. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  305. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  306. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  307. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  308. };
  309. enum {
  310. TPM_ACCESS_VALID = 1 << 7,
  311. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  312. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  313. TPM_ACCESS_REQUEST_USE = 1 << 1,
  314. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  315. };
  316. enum {
  317. TPM_STS_FAMILY_SHIFT = 26,
  318. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  319. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  320. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  321. TPM_STS_COMMAND_CANCEL = 1 << 24,
  322. TPM_STS_BURST_COUNT_SHIFT = 8,
  323. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  324. TPM_STS_VALID = 1 << 7,
  325. TPM_STS_COMMAND_READY = 1 << 6,
  326. TPM_STS_GO = 1 << 5,
  327. TPM_STS_DATA_AVAIL = 1 << 4,
  328. TPM_STS_DATA_EXPECT = 1 << 3,
  329. TPM_STS_SELF_TEST_DONE = 1 << 2,
  330. TPM_STS_RESPONSE_RETRY = 1 << 1,
  331. };
  332. enum {
  333. TPM_CMD_COUNT_OFFSET = 2,
  334. TPM_CMD_ORDINAL_OFFSET = 6,
  335. TPM_MAX_BUF_SIZE = 1260,
  336. };
  337. enum {
  338. /* Secure storage for firmware settings */
  339. TPM_HT_PCR = 0,
  340. TPM_HT_NV_INDEX,
  341. TPM_HT_HMAC_SESSION,
  342. TPM_HT_POLICY_SESSION,
  343. HR_SHIFT = 24,
  344. HR_PCR = TPM_HT_PCR << HR_SHIFT,
  345. HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
  346. HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
  347. HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
  348. };
  349. /**
  350. * Issue a TPM2_Startup command.
  351. *
  352. * @dev TPM device
  353. * @mode TPM startup mode
  354. *
  355. * @return code of the operation
  356. */
  357. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  358. /**
  359. * Issue a TPM2_SelfTest command.
  360. *
  361. * @dev TPM device
  362. * @full_test Asking to perform all tests or only the untested ones
  363. *
  364. * @return code of the operation
  365. */
  366. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  367. /**
  368. * Issue a TPM2_Clear command.
  369. *
  370. * @dev TPM device
  371. * @handle Handle
  372. * @pw Password
  373. * @pw_sz Length of the password
  374. *
  375. * @return code of the operation
  376. */
  377. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  378. const ssize_t pw_sz);
  379. /**
  380. * Issue a TPM_NV_DefineSpace command
  381. *
  382. * This allows a space to be defined with given attributes and policy
  383. *
  384. * @dev TPM device
  385. * @space_index index of the area
  386. * @space_size size of area in bytes
  387. * @nv_attributes TPM_NV_ATTRIBUTES of the area
  388. * @nv_policy policy to use
  389. * @nv_policy_size size of the policy
  390. * @return return code of the operation
  391. */
  392. u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
  393. size_t space_size, u32 nv_attributes,
  394. const u8 *nv_policy, size_t nv_policy_size);
  395. /**
  396. * Issue a TPM2_PCR_Extend command.
  397. *
  398. * @dev TPM device
  399. * @index Index of the PCR
  400. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  401. * @digest Value representing the event to be recorded
  402. * @digest_len len of the hash
  403. *
  404. * @return code of the operation
  405. */
  406. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  407. const u8 *digest, u32 digest_len);
  408. /**
  409. * Read data from the secure storage
  410. *
  411. * @dev TPM device
  412. * @index Index of data to read
  413. * @data Place to put data
  414. * @count Number of bytes of data
  415. * @return code of the operation
  416. */
  417. u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
  418. /**
  419. * Write data to the secure storage
  420. *
  421. * @dev TPM device
  422. * @index Index of data to write
  423. * @data Data to write
  424. * @count Number of bytes of data
  425. * @return code of the operation
  426. */
  427. u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
  428. u32 count);
  429. /**
  430. * Issue a TPM2_PCR_Read command.
  431. *
  432. * @dev TPM device
  433. * @idx Index of the PCR
  434. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  435. * @data Output buffer for contents of the named PCR
  436. * @updates Optional out parameter: number of updates for this PCR
  437. *
  438. * @return code of the operation
  439. */
  440. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  441. void *data, unsigned int *updates);
  442. /**
  443. * Issue a TPM2_GetCapability command. This implementation is limited
  444. * to query property index that is 4-byte wide.
  445. *
  446. * @dev TPM device
  447. * @capability Partition of capabilities
  448. * @property Further definition of capability, limited to be 4 bytes wide
  449. * @buf Output buffer for capability information
  450. * @prop_count Size of output buffer
  451. *
  452. * @return code of the operation
  453. */
  454. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  455. void *buf, size_t prop_count);
  456. /**
  457. * Issue a TPM2_DictionaryAttackLockReset command.
  458. *
  459. * @dev TPM device
  460. * @pw Password
  461. * @pw_sz Length of the password
  462. *
  463. * @return code of the operation
  464. */
  465. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  466. /**
  467. * Issue a TPM2_DictionaryAttackParameters command.
  468. *
  469. * @dev TPM device
  470. * @pw Password
  471. * @pw_sz Length of the password
  472. * @max_tries Count of authorizations before lockout
  473. * @recovery_time Time before decrementation of the failure count
  474. * @lockout_recovery Time to wait after a lockout
  475. *
  476. * @return code of the operation
  477. */
  478. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  479. const ssize_t pw_sz, unsigned int max_tries,
  480. unsigned int recovery_time,
  481. unsigned int lockout_recovery);
  482. /**
  483. * Issue a TPM2_HierarchyChangeAuth command.
  484. *
  485. * @dev TPM device
  486. * @handle Handle
  487. * @newpw New password
  488. * @newpw_sz Length of the new password
  489. * @oldpw Old password
  490. * @oldpw_sz Length of the old password
  491. *
  492. * @return code of the operation
  493. */
  494. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  495. const ssize_t newpw_sz, const char *oldpw,
  496. const ssize_t oldpw_sz);
  497. /**
  498. * Issue a TPM_PCR_SetAuthPolicy command.
  499. *
  500. * @dev TPM device
  501. * @pw Platform password
  502. * @pw_sz Length of the password
  503. * @index Index of the PCR
  504. * @digest New key to access the PCR
  505. *
  506. * @return code of the operation
  507. */
  508. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  509. const ssize_t pw_sz, u32 index, const char *key);
  510. /**
  511. * Issue a TPM_PCR_SetAuthValue command.
  512. *
  513. * @dev TPM device
  514. * @pw Platform password
  515. * @pw_sz Length of the password
  516. * @index Index of the PCR
  517. * @digest New key to access the PCR
  518. * @key_sz Length of the new key
  519. *
  520. * @return code of the operation
  521. */
  522. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  523. const ssize_t pw_sz, u32 index, const char *key,
  524. const ssize_t key_sz);
  525. /**
  526. * Issue a TPM2_GetRandom command.
  527. *
  528. * @dev TPM device
  529. * @param data output buffer for the random bytes
  530. * @param count size of output buffer
  531. *
  532. * @return return code of the operation
  533. */
  534. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  535. /**
  536. * Lock data in the TPM
  537. *
  538. * Once locked the data cannot be written until after a reboot
  539. *
  540. * @dev TPM device
  541. * @index Index of data to lock
  542. * @return code of the operation
  543. */
  544. u32 tpm2_write_lock(struct udevice *dev, u32 index);
  545. /**
  546. * Disable access to any platform data
  547. *
  548. * This can be called to close off access to the firmware data in the data,
  549. * before calling the kernel.
  550. *
  551. * @dev TPM device
  552. * @return code of the operation
  553. */
  554. u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
  555. #endif /* __TPM_V2_H */