mux.c 12 KB

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  1. /*
  2. * pinmux setup for siemens rut board
  3. *
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. * u-boot:/board/ti/am335x/mux.c
  9. *
  10. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/mux.h>
  18. #include <asm/io.h>
  19. #include <i2c.h>
  20. static struct module_pin_mux uart0_pin_mux[] = {
  21. {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
  22. {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
  23. {-1},
  24. };
  25. static struct module_pin_mux ddr_pin_mux[] = {
  26. {OFFSET(ddr_resetn), (MODE(0))},
  27. {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
  28. {OFFSET(ddr_ck), (MODE(0))},
  29. {OFFSET(ddr_nck), (MODE(0))},
  30. {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
  31. {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
  32. {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
  33. {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
  34. {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
  35. {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
  36. {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
  37. {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
  38. {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
  39. {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
  40. {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
  41. {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
  42. {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
  43. {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
  44. {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
  45. {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
  46. {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
  47. {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
  48. {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
  49. {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
  50. {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
  51. {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
  52. {OFFSET(ddr_odt), (MODE(0))},
  53. {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
  54. {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
  55. {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
  56. {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
  57. {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
  58. {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
  59. {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
  60. {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
  61. {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
  62. {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
  63. {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
  64. {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
  65. {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
  66. {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
  67. {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
  68. {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
  69. {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
  70. {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
  71. {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
  72. {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  73. {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
  74. {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
  75. {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
  76. {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
  77. {-1},
  78. };
  79. static struct module_pin_mux lcd_pin_mux[] = {
  80. {OFFSET(gpmc_ad8), (MODE(1))},
  81. {OFFSET(gpmc_ad9), (MODE(1))},
  82. {OFFSET(gpmc_ad10), (MODE(1))},
  83. {OFFSET(gpmc_ad11), (MODE(1))},
  84. {OFFSET(gpmc_ad12), (MODE(1))},
  85. {OFFSET(gpmc_ad13), (MODE(1))},
  86. {OFFSET(gpmc_ad14), (MODE(1))},
  87. {OFFSET(gpmc_ad15), (MODE(1))},
  88. {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
  89. {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
  90. {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
  91. {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
  92. {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
  93. {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
  94. {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
  95. {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
  96. {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
  97. {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
  98. {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
  99. {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
  100. {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
  101. {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
  102. {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
  103. {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
  104. {OFFSET(lcd_vsync), (MODE(0))},
  105. {OFFSET(lcd_hsync), (MODE(0))},
  106. {OFFSET(lcd_pclk), (MODE(0))},
  107. {OFFSET(lcd_ac_bias_en), (MODE(0))},
  108. {-1},
  109. };
  110. static struct module_pin_mux mmc0_pin_mux[] = {
  111. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
  112. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
  113. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
  114. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  115. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
  116. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
  117. {-1},
  118. };
  119. static struct module_pin_mux mii_pin_mux[] = {
  120. {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
  121. {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
  122. {OFFSET(mii1_txen), (MODE(1))},
  123. {OFFSET(mii1_txd1), (MODE(1))},
  124. {OFFSET(mii1_txd0), (MODE(1))},
  125. {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
  126. {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
  127. {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
  128. {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
  129. {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
  130. {-1},
  131. };
  132. static struct module_pin_mux gpio_pin_mux[] = {
  133. {OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
  134. {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
  135. {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
  136. {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
  137. {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
  138. {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
  139. {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
  140. {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
  141. {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
  142. {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
  143. {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
  144. {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
  145. {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
  146. {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
  147. {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
  148. {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
  149. {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
  150. {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
  151. {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
  152. {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
  153. {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
  154. {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
  155. {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
  156. {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
  157. {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
  158. {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
  159. {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
  160. {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
  161. {OFFSET(mcasp0_fsr), (MODE(7))},
  162. {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
  163. {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
  164. {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
  165. {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
  166. {-1},
  167. };
  168. static struct module_pin_mux i2c0_pin_mux[] = {
  169. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
  170. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
  171. {-1},
  172. };
  173. static struct module_pin_mux i2c1_pin_mux[] = {
  174. {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
  175. {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
  176. {-1},
  177. };
  178. static struct module_pin_mux usb0_pin_mux[] = {
  179. {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
  180. {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
  181. {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
  182. {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
  183. {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
  184. {OFFSET(usb0_drvvbus), (MODE(0))},
  185. {-1},
  186. };
  187. static struct module_pin_mux usb1_pin_mux[] = {
  188. {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
  189. {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
  190. {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
  191. {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
  192. {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
  193. {OFFSET(usb1_drvvbus), (MODE(0))},
  194. {-1},
  195. };
  196. static struct module_pin_mux spi0_pin_mux[] = {
  197. {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
  198. {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
  199. {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
  200. {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
  201. {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
  202. {-1},
  203. };
  204. static struct module_pin_mux spi1_pin_mux[] = {
  205. {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
  206. {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
  207. {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
  208. {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
  209. {-1},
  210. };
  211. static struct module_pin_mux jtag_pin_mux[] = {
  212. {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
  213. {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
  214. {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
  215. {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
  216. {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
  217. {-1},
  218. };
  219. static struct module_pin_mux nand_pin_mux[] = {
  220. {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
  221. {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
  222. {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
  223. {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
  224. {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
  225. {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
  226. {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
  227. {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
  228. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
  229. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
  230. {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
  231. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
  232. {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
  233. {-1},
  234. };
  235. static struct module_pin_mux ainx_pin_mux[] = {
  236. {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
  237. {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
  238. {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
  239. {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
  240. {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
  241. {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
  242. {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
  243. {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
  244. {-1},
  245. };
  246. static struct module_pin_mux rtc_pin_mux[] = {
  247. {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
  248. {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
  249. {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
  250. {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
  251. {-1},
  252. };
  253. static struct module_pin_mux gpmc_pin_mux[] = {
  254. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  255. {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
  256. {-1},
  257. };
  258. static struct module_pin_mux pmic_pin_mux[] = {
  259. {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
  260. {-1},
  261. };
  262. static struct module_pin_mux osc_pin_mux[] = {
  263. {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
  264. {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
  265. {-1},
  266. };
  267. static struct module_pin_mux pwm_pin_mux[] = {
  268. {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
  269. {OFFSET(gpmc_a2), (MODE(6))},
  270. {OFFSET(gpmc_a3), (MODE(6))},
  271. {-1},
  272. };
  273. static struct module_pin_mux emu_pin_mux[] = {
  274. {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
  275. {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
  276. {-1},
  277. };
  278. static struct module_pin_mux vref_pin_mux[] = {
  279. {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
  280. {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
  281. {-1},
  282. };
  283. static struct module_pin_mux misc_pin_mux[] = {
  284. {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
  285. {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
  286. {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
  287. {-1},
  288. };
  289. void enable_uart0_pin_mux(void)
  290. {
  291. configure_module_pin_mux(uart0_pin_mux);
  292. }
  293. void enable_i2c0_pin_mux(void)
  294. {
  295. configure_module_pin_mux(i2c0_pin_mux);
  296. }
  297. void enable_board_pin_mux(void)
  298. {
  299. configure_module_pin_mux(ddr_pin_mux);
  300. configure_module_pin_mux(lcd_pin_mux);
  301. configure_module_pin_mux(mmc0_pin_mux);
  302. configure_module_pin_mux(mii_pin_mux);
  303. configure_module_pin_mux(gpio_pin_mux);
  304. configure_module_pin_mux(i2c1_pin_mux);
  305. configure_module_pin_mux(usb0_pin_mux);
  306. configure_module_pin_mux(usb1_pin_mux);
  307. configure_module_pin_mux(spi0_pin_mux);
  308. configure_module_pin_mux(spi1_pin_mux);
  309. configure_module_pin_mux(jtag_pin_mux);
  310. configure_module_pin_mux(nand_pin_mux);
  311. configure_module_pin_mux(ainx_pin_mux);
  312. configure_module_pin_mux(rtc_pin_mux);
  313. configure_module_pin_mux(gpmc_pin_mux);
  314. configure_module_pin_mux(pmic_pin_mux);
  315. configure_module_pin_mux(osc_pin_mux);
  316. configure_module_pin_mux(pwm_pin_mux);
  317. configure_module_pin_mux(emu_pin_mux);
  318. configure_module_pin_mux(vref_pin_mux);
  319. configure_module_pin_mux(misc_pin_mux);
  320. }