mux.c 7.1 KB

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  1. /*
  2. * pinmux setup for siemens pxm2 board
  3. *
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. * u-boot:/board/ti/am335x/mux.c
  9. *
  10. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/mux.h>
  18. #include <asm/io.h>
  19. #include <i2c.h>
  20. #include "board.h"
  21. static struct module_pin_mux uart0_pin_mux[] = {
  22. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  23. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  24. {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
  25. {-1},
  26. };
  27. #ifdef CONFIG_NAND
  28. static struct module_pin_mux nand_pin_mux[] = {
  29. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  30. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  31. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  32. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  33. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  34. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  35. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  36. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  37. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  38. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  39. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  40. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  41. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  42. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  43. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  44. {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
  45. {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */
  46. {-1},
  47. };
  48. #endif
  49. static struct module_pin_mux i2c0_pin_mux[] = {
  50. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  51. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  52. {-1},
  53. };
  54. static struct module_pin_mux i2c1_pin_mux[] = {
  55. {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  56. {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  57. {-1},
  58. };
  59. #ifndef CONFIG_NO_ETH
  60. static struct module_pin_mux rgmii1_pin_mux[] = {
  61. {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  62. {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  63. {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  64. {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  65. {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  66. {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  67. {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  68. {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  69. {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  70. {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  71. {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  72. {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  73. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  74. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  75. {-1},
  76. };
  77. static struct module_pin_mux rgmii2_pin_mux[] = {
  78. {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
  79. {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
  80. {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
  81. {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
  82. {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
  83. {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
  84. {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
  85. {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
  86. {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
  87. {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
  88. {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
  89. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  90. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  91. {-1},
  92. };
  93. #endif
  94. #ifdef CONFIG_MMC
  95. static struct module_pin_mux mmc0_pin_mux[] = {
  96. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  97. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  98. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  99. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  100. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  101. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  102. {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
  103. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */
  104. {-1},
  105. };
  106. #endif
  107. static struct module_pin_mux lcdc_pin_mux[] = {
  108. {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */
  109. {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */
  110. {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */
  111. {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */
  112. {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */
  113. {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */
  114. {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */
  115. {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */
  116. {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */
  117. {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */
  118. {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */
  119. {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */
  120. {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */
  121. {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */
  122. {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */
  123. {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */
  124. {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */
  125. {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */
  126. {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */
  127. {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */
  128. {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */
  129. {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */
  130. {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */
  131. {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */
  132. {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */
  133. {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */
  134. {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
  135. {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */
  136. {-1},
  137. };
  138. static struct module_pin_mux ecap0_pin_mux[] = {
  139. {OFFSET(ecap0_in_pwm0_out), (MODE(0))},
  140. {-1},
  141. };
  142. static struct module_pin_mux gpio_pin_mux[] = {
  143. {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
  144. {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
  145. {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
  146. {-1},
  147. };
  148. void enable_i2c0_pin_mux(void)
  149. {
  150. configure_module_pin_mux(i2c0_pin_mux);
  151. }
  152. void enable_uart0_pin_mux(void)
  153. {
  154. configure_module_pin_mux(uart0_pin_mux);
  155. }
  156. void enable_board_pin_mux(void)
  157. {
  158. configure_module_pin_mux(uart0_pin_mux);
  159. configure_module_pin_mux(i2c1_pin_mux);
  160. #ifdef CONFIG_NAND
  161. configure_module_pin_mux(nand_pin_mux);
  162. #endif
  163. #ifndef CONFIG_NO_ETH
  164. configure_module_pin_mux(rgmii1_pin_mux);
  165. configure_module_pin_mux(rgmii2_pin_mux);
  166. #endif
  167. #ifdef CONFIG_MMC
  168. configure_module_pin_mux(mmc0_pin_mux);
  169. #endif
  170. configure_module_pin_mux(lcdc_pin_mux);
  171. configure_module_pin_mux(gpio_pin_mux);
  172. configure_module_pin_mux(ecap0_pin_mux);
  173. }