dpll-pro4.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013-2014 Panasonic Corporation
  4. * Copyright (C) 2015-2016 Socionext Inc.
  5. */
  6. #include <common.h>
  7. #include <linux/delay.h>
  8. #include <linux/errno.h>
  9. #include <linux/io.h>
  10. #include "../init.h"
  11. #include "../sc-regs.h"
  12. #undef DPLL_SSC_RATE_1PER
  13. int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
  14. {
  15. unsigned int dram_freq = bd->dram_freq;
  16. u32 tmp;
  17. /*
  18. * Set Frequency
  19. * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  20. * to FOUT ( DPLLCTRL.bit[29:20] )
  21. */
  22. tmp = readl(sc_base + SC_DPLLCTRL);
  23. tmp &= ~(0x000f0000);
  24. switch (dram_freq) {
  25. case 1333:
  26. tmp |= 0x000d0000;
  27. break;
  28. case 1600:
  29. tmp |= 0x000c0000;
  30. break;
  31. default:
  32. pr_err("Unsupported frequency");
  33. return -EINVAL;
  34. }
  35. /*
  36. * Set Moduration rate
  37. * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
  38. */
  39. #if defined(DPLL_SSC_RATE_1PER)
  40. tmp &= ~0x00008000;
  41. #else
  42. tmp |= 0x00008000;
  43. #endif
  44. writel(tmp, sc_base + SC_DPLLCTRL);
  45. tmp = readl(sc_base + SC_DPLLCTRL2);
  46. tmp |= SC_DPLLCTRL2_NRSTDS;
  47. writel(tmp, sc_base + SC_DPLLCTRL2);
  48. /* Wait until dpll gets stable */
  49. udelay(500);
  50. return 0;
  51. }