cpu.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/flow.h>
  10. #include <asm/arch/tegra.h>
  11. #include <asm/arch-tegra/clk_rst.h>
  12. #include <asm/arch-tegra/pmc.h>
  13. #include <asm/arch-tegra/tegra_i2c.h>
  14. #include <linux/delay.h>
  15. #include "../cpu.h"
  16. /* Tegra30-specific CPU init code */
  17. void tegra_i2c_ll_write_addr(uint addr, uint config)
  18. {
  19. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  20. writel(addr, &reg->cmd_addr0);
  21. writel(config, &reg->cnfg);
  22. }
  23. void tegra_i2c_ll_write_data(uint data, uint config)
  24. {
  25. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  26. writel(data, &reg->cmd_data1);
  27. writel(config, &reg->cnfg);
  28. }
  29. #define TPS62366A_I2C_ADDR 0xC0
  30. #define TPS62366A_SET1_REG 0x01
  31. #define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
  32. #define TPS62361B_I2C_ADDR 0xC0
  33. #define TPS62361B_SET3_REG 0x03
  34. #define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
  35. #define TPS65911_I2C_ADDR 0x5A
  36. #define TPS65911_VDDCTRL_OP_REG 0x28
  37. #define TPS65911_VDDCTRL_SR_REG 0x27
  38. #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
  39. #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
  40. #define I2C_SEND_2_BYTES 0x0A02
  41. static void enable_cpu_power_rail(void)
  42. {
  43. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  44. u32 reg;
  45. debug("enable_cpu_power_rail entry\n");
  46. reg = readl(&pmc->pmc_cntrl);
  47. reg |= CPUPWRREQ_OE;
  48. writel(reg, &pmc->pmc_cntrl);
  49. /* Set VDD_CORE to 1.200V. */
  50. #ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
  51. tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
  52. tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
  53. #endif
  54. #ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
  55. tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
  56. tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
  57. #endif
  58. udelay(1000);
  59. /*
  60. * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
  61. * First set VDD to 1.0125V, then enable the VDD regulator.
  62. */
  63. tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
  64. tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
  65. udelay(1000);
  66. tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
  67. udelay(10 * 1000);
  68. }
  69. /**
  70. * The T30 requires some special clock initialization, including setting up
  71. * the dvc i2c, turning on mselect and selecting the G CPU cluster
  72. */
  73. void t30_init_clocks(void)
  74. {
  75. struct clk_rst_ctlr *clkrst =
  76. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  77. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  78. u32 val;
  79. debug("t30_init_clocks entry\n");
  80. /* Set active CPU cluster to G */
  81. clrbits_le32(flow->cluster_control, 1 << 0);
  82. writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
  83. val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
  84. (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
  85. (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
  86. (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
  87. writel(val, &clkrst->crc_clk_sys_rate);
  88. /* Put i2c, mselect in reset and enable clocks */
  89. reset_set_enable(PERIPH_ID_DVC_I2C, 1);
  90. clock_set_enable(PERIPH_ID_DVC_I2C, 1);
  91. reset_set_enable(PERIPH_ID_MSELECT, 1);
  92. clock_set_enable(PERIPH_ID_MSELECT, 1);
  93. /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
  94. clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
  95. /*
  96. * Our high-level clock routines are not available prior to
  97. * relocation. We use the low-level functions which require a
  98. * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
  99. */
  100. clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
  101. /*
  102. * Give clocks time to stabilize, then take i2c and mselect out of
  103. * reset
  104. */
  105. udelay(1000);
  106. reset_set_enable(PERIPH_ID_DVC_I2C, 0);
  107. reset_set_enable(PERIPH_ID_MSELECT, 0);
  108. }
  109. static void set_cpu_running(int run)
  110. {
  111. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  112. debug("set_cpu_running entry, run = %d\n", run);
  113. writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
  114. }
  115. void start_cpu(u32 reset_vector)
  116. {
  117. debug("start_cpu entry, reset_vector = %x\n", reset_vector);
  118. t30_init_clocks();
  119. /* Enable VDD_CPU */
  120. enable_cpu_power_rail();
  121. set_cpu_running(0);
  122. /* Hold the CPUs in reset */
  123. reset_A9_cpu(1);
  124. /* Disable the CPU clock */
  125. enable_cpu_clock(0);
  126. /* Enable CoreSight */
  127. clock_enable_coresight(1);
  128. /*
  129. * Set the entry point for CPU execution from reset,
  130. * if it's a non-zero value.
  131. */
  132. if (reset_vector)
  133. writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
  134. /* Enable the CPU clock */
  135. enable_cpu_clock(1);
  136. /* If the CPU doesn't already have power, power it up */
  137. powerup_cpu();
  138. /* Take the CPU out of reset */
  139. reset_A9_cpu(0);
  140. set_cpu_running(1);
  141. }