xusb-padctl.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <dm/of_access.h>
  10. #include <dm/ofnode.h>
  11. #include <linux/delay.h>
  12. #include "../xusb-padctl-common.h"
  13. #include <asm/arch/clock.h>
  14. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. enum tegra210_function {
  17. TEGRA210_FUNC_SNPS,
  18. TEGRA210_FUNC_XUSB,
  19. TEGRA210_FUNC_UART,
  20. TEGRA210_FUNC_PCIE_X1,
  21. TEGRA210_FUNC_PCIE_X4,
  22. TEGRA210_FUNC_USB3,
  23. TEGRA210_FUNC_SATA,
  24. TEGRA210_FUNC_RSVD,
  25. };
  26. static const char *const tegra210_functions[] = {
  27. "snps",
  28. "xusb",
  29. "uart",
  30. "pcie-x1",
  31. "pcie-x4",
  32. "usb3",
  33. "sata",
  34. "rsvd",
  35. };
  36. static const unsigned int tegra210_otg_functions[] = {
  37. TEGRA210_FUNC_SNPS,
  38. TEGRA210_FUNC_XUSB,
  39. TEGRA210_FUNC_UART,
  40. TEGRA210_FUNC_RSVD,
  41. };
  42. static const unsigned int tegra210_usb_functions[] = {
  43. TEGRA210_FUNC_SNPS,
  44. TEGRA210_FUNC_XUSB,
  45. };
  46. static const unsigned int tegra210_pci_functions[] = {
  47. TEGRA210_FUNC_PCIE_X1,
  48. TEGRA210_FUNC_USB3,
  49. TEGRA210_FUNC_SATA,
  50. TEGRA210_FUNC_PCIE_X4,
  51. };
  52. #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
  53. { \
  54. .name = _name, \
  55. .offset = _offset, \
  56. .shift = _shift, \
  57. .mask = _mask, \
  58. .iddq = _iddq, \
  59. .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
  60. .funcs = tegra210_##_funcs##_functions, \
  61. }
  62. static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
  63. TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
  64. TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
  65. TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
  66. TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg),
  67. TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
  68. TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
  69. TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
  70. TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci),
  71. TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci),
  72. TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci),
  73. TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci),
  74. TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci),
  75. TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci),
  76. TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci),
  77. TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci),
  78. };
  79. #define XUSB_PADCTL_ELPG_PROGRAM 0x024
  80. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
  81. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
  82. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
  83. static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
  84. {
  85. u32 value;
  86. if (padctl->enable++ > 0)
  87. return 0;
  88. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  89. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  90. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  91. udelay(100);
  92. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  93. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  94. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  95. udelay(100);
  96. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  97. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  98. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  99. return 0;
  100. }
  101. static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
  102. {
  103. u32 value;
  104. if (padctl->enable == 0) {
  105. pr_err("unbalanced enable/disable");
  106. return 0;
  107. }
  108. if (--padctl->enable > 0)
  109. return 0;
  110. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  111. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  112. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  113. udelay(100);
  114. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  115. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  116. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  117. udelay(100);
  118. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  119. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  120. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  121. return 0;
  122. }
  123. static int phy_prepare(struct tegra_xusb_phy *phy)
  124. {
  125. int err;
  126. err = tegra_xusb_padctl_enable(phy->padctl);
  127. if (err < 0)
  128. return err;
  129. reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
  130. return 0;
  131. }
  132. static int phy_unprepare(struct tegra_xusb_phy *phy)
  133. {
  134. reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
  135. return tegra_xusb_padctl_disable(phy->padctl);
  136. }
  137. #define XUSB_PADCTL_USB3_PAD_MUX 0x28
  138. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
  139. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
  140. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
  141. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
  142. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
  143. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
  144. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
  145. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
  146. #define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
  147. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
  148. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
  149. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
  150. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
  151. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
  152. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
  153. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
  154. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
  155. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
  156. #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
  157. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
  158. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
  159. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
  160. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
  161. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
  162. #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
  163. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
  164. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
  165. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
  166. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
  167. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
  168. #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
  169. #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
  170. #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
  171. #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
  172. #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
  173. #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
  174. #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
  175. #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
  176. #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
  177. #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
  178. #define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
  179. #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
  180. #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
  181. #define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
  182. #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
  183. static int pcie_phy_enable(struct tegra_xusb_phy *phy)
  184. {
  185. struct tegra_xusb_padctl *padctl = phy->padctl;
  186. unsigned long start;
  187. u32 value;
  188. debug("> %s(phy=%p)\n", __func__, phy);
  189. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  190. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
  191. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
  192. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  193. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
  194. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
  195. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
  196. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
  197. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  198. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
  199. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  200. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  201. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
  202. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  203. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  204. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
  205. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  206. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
  207. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
  208. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
  209. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
  210. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
  211. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
  212. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  213. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
  214. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
  215. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
  216. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  217. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  218. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
  219. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  220. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  221. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
  222. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  223. udelay(1);
  224. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
  225. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
  226. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
  227. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  228. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
  229. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  230. debug(" waiting for calibration\n");
  231. start = get_timer(0);
  232. while (get_timer(start) < 250) {
  233. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  234. if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
  235. break;
  236. }
  237. if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
  238. debug(" timeout\n");
  239. return -ETIMEDOUT;
  240. }
  241. debug(" done\n");
  242. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  243. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
  244. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  245. debug(" waiting for calibration to stop\n");
  246. start = get_timer(0);
  247. while (get_timer(start) < 250) {
  248. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
  249. if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
  250. break;
  251. }
  252. if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
  253. debug(" timeout\n");
  254. return -ETIMEDOUT;
  255. }
  256. debug(" done\n");
  257. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  258. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
  259. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  260. debug(" waiting for PLL to lock...\n");
  261. start = get_timer(0);
  262. while (get_timer(start) < 250) {
  263. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  264. if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
  265. break;
  266. }
  267. if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
  268. debug(" timeout\n");
  269. return -ETIMEDOUT;
  270. }
  271. debug(" done\n");
  272. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  273. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
  274. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
  275. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  276. debug(" waiting for register calibration...\n");
  277. start = get_timer(0);
  278. while (get_timer(start) < 250) {
  279. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  280. if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
  281. break;
  282. }
  283. if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
  284. debug(" timeout\n");
  285. return -ETIMEDOUT;
  286. }
  287. debug(" done\n");
  288. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  289. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
  290. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  291. debug(" waiting for register calibration to stop...\n");
  292. start = get_timer(0);
  293. while (get_timer(start) < 250) {
  294. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  295. if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
  296. break;
  297. }
  298. if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
  299. debug(" timeout\n");
  300. return -ETIMEDOUT;
  301. }
  302. debug(" done\n");
  303. value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  304. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
  305. padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
  306. debug("< %s()\n", __func__);
  307. return 0;
  308. }
  309. static int pcie_phy_disable(struct tegra_xusb_phy *phy)
  310. {
  311. return 0;
  312. }
  313. static const struct tegra_xusb_phy_ops pcie_phy_ops = {
  314. .prepare = phy_prepare,
  315. .enable = pcie_phy_enable,
  316. .disable = pcie_phy_disable,
  317. .unprepare = phy_unprepare,
  318. };
  319. static struct tegra_xusb_phy tegra210_phys[] = {
  320. {
  321. .type = TEGRA_XUSB_PADCTL_PCIE,
  322. .ops = &pcie_phy_ops,
  323. .padctl = &padctl,
  324. },
  325. };
  326. static const struct tegra_xusb_padctl_soc tegra210_socdata = {
  327. .lanes = tegra210_lanes,
  328. .num_lanes = ARRAY_SIZE(tegra210_lanes),
  329. .functions = tegra210_functions,
  330. .num_functions = ARRAY_SIZE(tegra210_functions),
  331. .phys = tegra210_phys,
  332. .num_phys = ARRAY_SIZE(tegra210_phys),
  333. };
  334. void tegra_xusb_padctl_init(void)
  335. {
  336. ofnode nodes[1];
  337. int count = 0;
  338. int ret;
  339. debug("%s: start\n", __func__);
  340. if (of_live_active()) {
  341. struct device_node *np = of_find_compatible_node(NULL, NULL,
  342. "nvidia,tegra210-xusb-padctl");
  343. debug("np=%p\n", np);
  344. if (np) {
  345. nodes[0] = np_to_ofnode(np);
  346. count = 1;
  347. }
  348. } else {
  349. int node_offsets[1];
  350. int i;
  351. count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
  352. COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
  353. node_offsets, ARRAY_SIZE(node_offsets));
  354. for (i = 0; i < count; i++)
  355. nodes[i] = offset_to_ofnode(node_offsets[i]);
  356. }
  357. ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
  358. debug("%s: done, ret=%d\n", __func__, ret);
  359. }
  360. void tegra_xusb_padctl_exit(void)
  361. {
  362. u32 value;
  363. debug("> %s\n", __func__);
  364. value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
  365. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
  366. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
  367. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
  368. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
  369. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
  370. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
  371. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
  372. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
  373. value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
  374. padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
  375. value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  376. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
  377. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
  378. value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
  379. value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
  380. padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
  381. reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
  382. while (padctl.enable)
  383. tegra_xusb_padctl_disable(&padctl);
  384. debug("< %s()\n", __func__);
  385. }