clock.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra124 Clock control functions */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/sysctr.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <asm/arch-tegra/timer.h>
  16. #include <div64.h>
  17. #include <fdtdec.h>
  18. #include <linux/delay.h>
  19. /*
  20. * Clock types that we can use as a source. The Tegra124 has muxes for the
  21. * peripheral clocks, and in most cases there are four options for the clock
  22. * source. This gives us a clock 'type' and exploits what commonality exists
  23. * in the device.
  24. *
  25. * Letters are obvious, except for T which means CLK_M, and S which means the
  26. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  27. * datasheet) and PLL_M are different things. The former is the basic
  28. * clock supplied to the SOC from an external oscillator. The latter is the
  29. * memory clock PLL.
  30. *
  31. * See definitions in clock_id in the header file.
  32. */
  33. enum clock_type_id {
  34. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  35. CLOCK_TYPE_MCPA, /* and so on */
  36. CLOCK_TYPE_MCPT,
  37. CLOCK_TYPE_PCM,
  38. CLOCK_TYPE_PCMT,
  39. CLOCK_TYPE_PDCT,
  40. CLOCK_TYPE_ACPT,
  41. CLOCK_TYPE_ASPTE,
  42. CLOCK_TYPE_PMDACD2T,
  43. CLOCK_TYPE_PCST,
  44. CLOCK_TYPE_DP,
  45. CLOCK_TYPE_PC2CC3M,
  46. CLOCK_TYPE_PC2CC3S_T,
  47. CLOCK_TYPE_PC2CC3M_T,
  48. CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
  49. CLOCK_TYPE_MC2CC3P_A,
  50. CLOCK_TYPE_M,
  51. CLOCK_TYPE_MCPTM2C2C3,
  52. CLOCK_TYPE_PC2CC3T_S,
  53. CLOCK_TYPE_AC2CC3P_TS2,
  54. CLOCK_TYPE_COUNT,
  55. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  56. };
  57. enum {
  58. CLOCK_MAX_MUX = 8 /* number of source options for each clock */
  59. };
  60. /*
  61. * Clock source mux for each clock type. This just converts our enum into
  62. * a list of mux sources for use by the code.
  63. *
  64. * Note:
  65. * The extra column in each clock source array is used to store the mask
  66. * bits in its register for the source.
  67. */
  68. #define CLK(x) CLOCK_ID_ ## x
  69. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  70. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M),
  71. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  72. MASK_BITS_31_30},
  73. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
  74. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  75. MASK_BITS_31_30},
  76. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  77. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  78. MASK_BITS_31_30},
  79. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
  80. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  81. MASK_BITS_31_30},
  82. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  83. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  84. MASK_BITS_31_30},
  85. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
  86. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  87. MASK_BITS_31_30},
  88. { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  89. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  90. MASK_BITS_31_30},
  91. { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
  92. CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
  93. MASK_BITS_31_29},
  94. { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
  95. CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
  96. MASK_BITS_31_29},
  97. { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
  98. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  99. MASK_BITS_31_28},
  100. /* CLOCK_TYPE_DP */
  101. { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  102. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  103. MASK_BITS_31_28},
  104. /* Additional clock types on Tegra114+ */
  105. /* CLOCK_TYPE_PC2CC3M */
  106. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  107. CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  108. MASK_BITS_31_29},
  109. /* CLOCK_TYPE_PC2CC3S_T */
  110. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  111. CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
  112. MASK_BITS_31_29},
  113. /* CLOCK_TYPE_PC2CC3M_T */
  114. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  115. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  116. MASK_BITS_31_29},
  117. /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
  118. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  119. CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
  120. MASK_BITS_31_29},
  121. /* CLOCK_TYPE_MC2CC3P_A */
  122. { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  123. CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
  124. MASK_BITS_31_29},
  125. /* CLOCK_TYPE_M */
  126. { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
  127. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  128. MASK_BITS_31_30},
  129. /* CLOCK_TYPE_MCPTM2C2C3 */
  130. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  131. CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
  132. MASK_BITS_31_29},
  133. /* CLOCK_TYPE_PC2CC3T_S */
  134. { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  135. CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
  136. MASK_BITS_31_29},
  137. /* CLOCK_TYPE_AC2CC3P_TS2 */
  138. { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
  139. CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
  140. MASK_BITS_31_29},
  141. };
  142. /*
  143. * Clock type for each peripheral clock source. We put the name in each
  144. * record just so it is easy to match things up
  145. */
  146. #define TYPE(name, type) type
  147. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  148. /* 0x00 */
  149. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  150. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  151. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  152. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
  153. TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
  154. TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
  155. TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
  156. TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
  157. /* 0x08 */
  158. TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
  159. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
  160. TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
  161. TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
  162. TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
  163. TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
  164. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
  165. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
  166. /* 0x10 */
  167. TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
  168. TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
  169. TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
  170. TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
  171. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
  172. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
  173. TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
  174. TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
  175. /* 0x18 */
  176. TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
  177. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
  178. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
  179. TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
  180. TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
  181. TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
  182. TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
  183. TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
  184. /* 0x20 */
  185. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
  186. TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
  187. TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
  188. TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
  189. TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
  190. TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
  191. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
  192. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
  193. /* 0x28 */
  194. TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
  195. TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
  196. TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
  197. TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
  198. TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
  199. TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
  200. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
  201. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
  202. /* 0x30 */
  203. TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
  204. TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
  205. TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
  206. TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
  207. TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
  208. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
  209. TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
  210. TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
  211. /* 0x38 */
  212. TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
  213. TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
  214. TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
  215. TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
  216. TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
  217. TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
  218. TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
  219. TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
  220. /* 0x40 */
  221. TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
  222. TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
  223. TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
  224. TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
  225. TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
  226. TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
  227. TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
  228. TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
  229. /* 0x48 */
  230. TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
  231. TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
  232. TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
  233. TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
  234. TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
  235. TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
  236. TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
  237. TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
  238. /* 0x50 */
  239. TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
  240. TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
  241. TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
  242. TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
  243. TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
  244. TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
  245. TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
  246. TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
  247. /* 0x58 */
  248. TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
  249. TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
  250. TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
  251. TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
  252. TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
  253. TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
  254. TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
  255. TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
  256. /* 0x60 */
  257. TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
  258. TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
  259. TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
  260. TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
  261. TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
  262. TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
  263. TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
  264. TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
  265. /* 0x68 */
  266. TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
  267. TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
  268. TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
  269. TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
  270. TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
  271. TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
  272. TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
  273. TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
  274. /* 0x70 */
  275. TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
  276. TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
  277. TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
  278. TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
  279. TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
  280. TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
  281. TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
  282. TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
  283. /* 0x78 */
  284. TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
  285. TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
  286. TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
  287. TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
  288. TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
  289. TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
  290. TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
  291. TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
  292. };
  293. /*
  294. * This array translates a periph_id to a periphc_internal_id
  295. *
  296. * Not present/matched up:
  297. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  298. * SPDIF - which is both 0x08 and 0x0c
  299. *
  300. */
  301. #define NONE(name) (-1)
  302. #define OFFSET(name, value) PERIPHC_ ## name
  303. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  304. /* Low word: 31:0 */
  305. NONE(CPU),
  306. NONE(COP),
  307. NONE(TRIGSYS),
  308. NONE(ISPB),
  309. NONE(RESERVED4),
  310. NONE(TMR),
  311. PERIPHC_UART1,
  312. PERIPHC_UART2, /* and vfir 0x68 */
  313. /* 8 */
  314. NONE(GPIO),
  315. PERIPHC_SDMMC2,
  316. PERIPHC_SPDIF_IN,
  317. PERIPHC_I2S1,
  318. PERIPHC_I2C1,
  319. NONE(RESERVED13),
  320. PERIPHC_SDMMC1,
  321. PERIPHC_SDMMC4,
  322. /* 16 */
  323. NONE(TCW),
  324. PERIPHC_PWM,
  325. PERIPHC_I2S2,
  326. NONE(RESERVED19),
  327. PERIPHC_VI,
  328. NONE(RESERVED21),
  329. NONE(USBD),
  330. NONE(ISP),
  331. /* 24 */
  332. NONE(RESERVED24),
  333. NONE(RESERVED25),
  334. PERIPHC_DISP2,
  335. PERIPHC_DISP1,
  336. PERIPHC_HOST1X,
  337. NONE(VCP),
  338. PERIPHC_I2S0,
  339. NONE(CACHE2),
  340. /* Middle word: 63:32 */
  341. NONE(MEM),
  342. NONE(AHBDMA),
  343. NONE(APBDMA),
  344. NONE(RESERVED35),
  345. NONE(RESERVED36),
  346. NONE(STAT_MON),
  347. NONE(RESERVED38),
  348. NONE(FUSE),
  349. /* 40 */
  350. NONE(KFUSE),
  351. PERIPHC_SBC1, /* SBCx = SPIx */
  352. PERIPHC_NOR,
  353. NONE(RESERVED43),
  354. PERIPHC_SBC2,
  355. NONE(XIO),
  356. PERIPHC_SBC3,
  357. PERIPHC_I2C5,
  358. /* 48 */
  359. NONE(DSI),
  360. NONE(RESERVED49),
  361. PERIPHC_HSI,
  362. PERIPHC_HDMI,
  363. NONE(CSI),
  364. NONE(RESERVED53),
  365. PERIPHC_I2C2,
  366. PERIPHC_UART3,
  367. /* 56 */
  368. NONE(MIPI_CAL),
  369. PERIPHC_EMC,
  370. NONE(USB2),
  371. NONE(USB3),
  372. NONE(RESERVED60),
  373. PERIPHC_VDE,
  374. NONE(BSEA),
  375. NONE(BSEV),
  376. /* Upper word 95:64 */
  377. NONE(RESERVED64),
  378. PERIPHC_UART4,
  379. PERIPHC_UART5,
  380. PERIPHC_I2C3,
  381. PERIPHC_SBC4,
  382. PERIPHC_SDMMC3,
  383. NONE(PCIE),
  384. PERIPHC_OWR,
  385. /* 72 */
  386. NONE(AFI),
  387. PERIPHC_CSITE,
  388. NONE(PCIEXCLK),
  389. NONE(AVPUCQ),
  390. NONE(LA),
  391. NONE(TRACECLKIN),
  392. NONE(SOC_THERM),
  393. NONE(DTV),
  394. /* 80 */
  395. NONE(RESERVED80),
  396. PERIPHC_I2CSLOW,
  397. NONE(DSIB),
  398. PERIPHC_TSEC,
  399. NONE(RESERVED84),
  400. NONE(RESERVED85),
  401. NONE(RESERVED86),
  402. NONE(EMUCIF),
  403. /* 88 */
  404. NONE(RESERVED88),
  405. NONE(XUSB_HOST),
  406. NONE(RESERVED90),
  407. PERIPHC_MSENC,
  408. NONE(RESERVED92),
  409. NONE(RESERVED93),
  410. NONE(RESERVED94),
  411. NONE(XUSB_DEV),
  412. /* V word: 31:0 */
  413. NONE(CPUG),
  414. NONE(CPULP),
  415. NONE(V_RESERVED2),
  416. PERIPHC_MSELECT,
  417. NONE(V_RESERVED4),
  418. PERIPHC_I2S3,
  419. PERIPHC_I2S4,
  420. PERIPHC_I2C4,
  421. /* 104 */
  422. PERIPHC_SBC5,
  423. PERIPHC_SBC6,
  424. PERIPHC_AUDIO,
  425. NONE(APBIF),
  426. PERIPHC_DAM0,
  427. PERIPHC_DAM1,
  428. PERIPHC_DAM2,
  429. PERIPHC_HDA2CODEC2X,
  430. /* 112 */
  431. NONE(ATOMICS),
  432. NONE(V_RESERVED17),
  433. NONE(V_RESERVED18),
  434. NONE(V_RESERVED19),
  435. NONE(V_RESERVED20),
  436. NONE(V_RESERVED21),
  437. NONE(V_RESERVED22),
  438. PERIPHC_ACTMON,
  439. /* 120 */
  440. PERIPHC_EXTPERIPH1,
  441. NONE(EXTPERIPH2),
  442. NONE(EXTPERIPH3),
  443. NONE(OOB),
  444. PERIPHC_SATA,
  445. PERIPHC_HDA,
  446. NONE(TZRAM),
  447. NONE(SE),
  448. /* W word: 31:0 */
  449. NONE(HDA2HDMICODEC),
  450. NONE(SATACOLD),
  451. NONE(W_RESERVED2),
  452. NONE(W_RESERVED3),
  453. NONE(W_RESERVED4),
  454. NONE(W_RESERVED5),
  455. NONE(W_RESERVED6),
  456. NONE(W_RESERVED7),
  457. /* 136 */
  458. NONE(CEC),
  459. NONE(W_RESERVED9),
  460. NONE(W_RESERVED10),
  461. NONE(W_RESERVED11),
  462. NONE(W_RESERVED12),
  463. NONE(W_RESERVED13),
  464. NONE(XUSB_PADCTL),
  465. NONE(W_RESERVED15),
  466. /* 144 */
  467. NONE(W_RESERVED16),
  468. NONE(W_RESERVED17),
  469. NONE(W_RESERVED18),
  470. NONE(W_RESERVED19),
  471. NONE(W_RESERVED20),
  472. NONE(ENTROPY),
  473. NONE(DDS),
  474. NONE(W_RESERVED23),
  475. /* 152 */
  476. NONE(DP2),
  477. NONE(AMX0),
  478. NONE(ADX0),
  479. NONE(DVFS),
  480. NONE(XUSB_SS),
  481. NONE(W_RESERVED29),
  482. NONE(W_RESERVED30),
  483. NONE(W_RESERVED31),
  484. /* X word: 31:0 */
  485. NONE(SPARE),
  486. NONE(X_RESERVED1),
  487. NONE(X_RESERVED2),
  488. NONE(X_RESERVED3),
  489. NONE(CAM_MCLK),
  490. NONE(CAM_MCLK2),
  491. PERIPHC_I2C6,
  492. NONE(X_RESERVED7),
  493. /* 168 */
  494. NONE(X_RESERVED8),
  495. NONE(X_RESERVED9),
  496. NONE(X_RESERVED10),
  497. NONE(VIM2_CLK),
  498. NONE(X_RESERVED12),
  499. NONE(X_RESERVED13),
  500. NONE(EMC_DLL),
  501. NONE(X_RESERVED15),
  502. /* 176 */
  503. NONE(HDMI_AUDIO),
  504. NONE(CLK72MHZ),
  505. NONE(VIC),
  506. NONE(X_RESERVED19),
  507. NONE(ADX1),
  508. NONE(DPAUX),
  509. PERIPHC_SOR,
  510. NONE(X_RESERVED23),
  511. /* 184 */
  512. NONE(GPU),
  513. NONE(AMX1),
  514. NONE(X_RESERVED26),
  515. NONE(X_RESERVED27),
  516. NONE(X_RESERVED28),
  517. NONE(X_RESERVED29),
  518. NONE(X_RESERVED30),
  519. NONE(X_RESERVED31),
  520. };
  521. /*
  522. * PLL divider shift/mask tables for all PLL IDs.
  523. */
  524. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  525. /*
  526. * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
  527. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
  528. * If lock_ena or lock_det are >31, they're not used in that PLL.
  529. */
  530. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
  531. .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
  532. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  533. .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  534. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  535. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
  536. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  537. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
  538. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
  539. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
  540. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  541. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
  542. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
  543. .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
  544. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  545. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  546. { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  547. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
  548. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
  549. .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
  550. };
  551. /*
  552. * Get the oscillator frequency, from the corresponding hardware configuration
  553. * field. Note that Tegra30+ support 3 new higher freqs, but we map back
  554. * to the old T20 freqs. Support for the higher oscillators is TBD.
  555. */
  556. enum clock_osc_freq clock_get_osc_freq(void)
  557. {
  558. struct clk_rst_ctlr *clkrst =
  559. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  560. u32 reg;
  561. reg = readl(&clkrst->crc_osc_ctrl);
  562. reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  563. if (reg & 1) /* one of the newer freqs */
  564. printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
  565. return reg >> 2; /* Map to most common (T20) freqs */
  566. }
  567. /* Returns a pointer to the clock source register for a peripheral */
  568. u32 *get_periph_source_reg(enum periph_id periph_id)
  569. {
  570. struct clk_rst_ctlr *clkrst =
  571. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  572. enum periphc_internal_id internal_id;
  573. /* Coresight is a special case */
  574. if (periph_id == PERIPH_ID_CSI)
  575. return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
  576. assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
  577. internal_id = periph_id_to_internal_id[periph_id];
  578. assert(internal_id != -1);
  579. if (internal_id >= PERIPHC_X_FIRST) {
  580. internal_id -= PERIPHC_X_FIRST;
  581. return &clkrst->crc_clk_src_x[internal_id];
  582. } else if (internal_id >= PERIPHC_VW_FIRST) {
  583. internal_id -= PERIPHC_VW_FIRST;
  584. return &clkrst->crc_clk_src_vw[internal_id];
  585. } else {
  586. return &clkrst->crc_clk_src[internal_id];
  587. }
  588. }
  589. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  590. int *divider_bits, int *type)
  591. {
  592. enum periphc_internal_id internal_id;
  593. if (!clock_periph_id_isvalid(periph_id))
  594. return -1;
  595. internal_id = periph_id_to_internal_id[periph_id];
  596. if (!periphc_internal_id_isvalid(internal_id))
  597. return -1;
  598. *type = clock_periph_type[internal_id];
  599. if (!clock_type_id_isvalid(*type))
  600. return -1;
  601. *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
  602. if (*type == CLOCK_TYPE_PC2CC3M_T16)
  603. *divider_bits = 16;
  604. else
  605. *divider_bits = 8;
  606. return 0;
  607. }
  608. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  609. {
  610. enum periphc_internal_id internal_id;
  611. int type;
  612. if (!clock_periph_id_isvalid(periph_id))
  613. return CLOCK_ID_NONE;
  614. internal_id = periph_id_to_internal_id[periph_id];
  615. if (!periphc_internal_id_isvalid(internal_id))
  616. return CLOCK_ID_NONE;
  617. type = clock_periph_type[internal_id];
  618. if (!clock_type_id_isvalid(type))
  619. return CLOCK_ID_NONE;
  620. return clock_source[type][source];
  621. }
  622. /**
  623. * Given a peripheral ID and the required source clock, this returns which
  624. * value should be programmed into the source mux for that peripheral.
  625. *
  626. * There is special code here to handle the one source type with 5 sources.
  627. *
  628. * @param periph_id peripheral to start
  629. * @param source PLL id of required parent clock
  630. * @param mux_bits Set to number of bits in mux register: 2 or 4
  631. * @param divider_bits Set to number of divider bits (8 or 16)
  632. * @return mux value (0-4, or -1 if not found)
  633. */
  634. int get_periph_clock_source(enum periph_id periph_id,
  635. enum clock_id parent, int *mux_bits, int *divider_bits)
  636. {
  637. enum clock_type_id type;
  638. int mux, err;
  639. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  640. assert(!err);
  641. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  642. if (clock_source[type][mux] == parent)
  643. return mux;
  644. /* if we get here, either us or the caller has made a mistake */
  645. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  646. parent);
  647. return -1;
  648. }
  649. void clock_set_enable(enum periph_id periph_id, int enable)
  650. {
  651. struct clk_rst_ctlr *clkrst =
  652. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  653. u32 *clk;
  654. u32 reg;
  655. /* Enable/disable the clock to this peripheral */
  656. assert(clock_periph_id_isvalid(periph_id));
  657. if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
  658. clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  659. else if ((int)periph_id < PERIPH_ID_X_FIRST)
  660. clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
  661. else
  662. clk = &clkrst->crc_clk_out_enb_x;
  663. reg = readl(clk);
  664. if (enable)
  665. reg |= PERIPH_MASK(periph_id);
  666. else
  667. reg &= ~PERIPH_MASK(periph_id);
  668. writel(reg, clk);
  669. }
  670. void reset_set_enable(enum periph_id periph_id, int enable)
  671. {
  672. struct clk_rst_ctlr *clkrst =
  673. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  674. u32 *reset;
  675. u32 reg;
  676. /* Enable/disable reset to the peripheral */
  677. assert(clock_periph_id_isvalid(periph_id));
  678. if (periph_id < PERIPH_ID_VW_FIRST)
  679. reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  680. else if ((int)periph_id < PERIPH_ID_X_FIRST)
  681. reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
  682. else
  683. reset = &clkrst->crc_rst_devices_x;
  684. reg = readl(reset);
  685. if (enable)
  686. reg |= PERIPH_MASK(periph_id);
  687. else
  688. reg &= ~PERIPH_MASK(periph_id);
  689. writel(reg, reset);
  690. }
  691. #if CONFIG_IS_ENABLED(OF_CONTROL)
  692. /*
  693. * Convert a device tree clock ID to our peripheral ID. They are mostly
  694. * the same but we are very cautious so we check that a valid clock ID is
  695. * provided.
  696. *
  697. * @param clk_id Clock ID according to tegra124 device tree binding
  698. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  699. */
  700. enum periph_id clk_id_to_periph_id(int clk_id)
  701. {
  702. if (clk_id > PERIPH_ID_COUNT)
  703. return PERIPH_ID_NONE;
  704. switch (clk_id) {
  705. case PERIPH_ID_RESERVED4:
  706. case PERIPH_ID_RESERVED25:
  707. case PERIPH_ID_RESERVED35:
  708. case PERIPH_ID_RESERVED36:
  709. case PERIPH_ID_RESERVED38:
  710. case PERIPH_ID_RESERVED43:
  711. case PERIPH_ID_RESERVED49:
  712. case PERIPH_ID_RESERVED53:
  713. case PERIPH_ID_RESERVED64:
  714. case PERIPH_ID_RESERVED84:
  715. case PERIPH_ID_RESERVED85:
  716. case PERIPH_ID_RESERVED86:
  717. case PERIPH_ID_RESERVED88:
  718. case PERIPH_ID_RESERVED90:
  719. case PERIPH_ID_RESERVED92:
  720. case PERIPH_ID_RESERVED93:
  721. case PERIPH_ID_RESERVED94:
  722. case PERIPH_ID_V_RESERVED2:
  723. case PERIPH_ID_V_RESERVED4:
  724. case PERIPH_ID_V_RESERVED17:
  725. case PERIPH_ID_V_RESERVED18:
  726. case PERIPH_ID_V_RESERVED19:
  727. case PERIPH_ID_V_RESERVED20:
  728. case PERIPH_ID_V_RESERVED21:
  729. case PERIPH_ID_V_RESERVED22:
  730. case PERIPH_ID_W_RESERVED2:
  731. case PERIPH_ID_W_RESERVED3:
  732. case PERIPH_ID_W_RESERVED4:
  733. case PERIPH_ID_W_RESERVED5:
  734. case PERIPH_ID_W_RESERVED6:
  735. case PERIPH_ID_W_RESERVED7:
  736. case PERIPH_ID_W_RESERVED9:
  737. case PERIPH_ID_W_RESERVED10:
  738. case PERIPH_ID_W_RESERVED11:
  739. case PERIPH_ID_W_RESERVED12:
  740. case PERIPH_ID_W_RESERVED13:
  741. case PERIPH_ID_W_RESERVED15:
  742. case PERIPH_ID_W_RESERVED16:
  743. case PERIPH_ID_W_RESERVED17:
  744. case PERIPH_ID_W_RESERVED18:
  745. case PERIPH_ID_W_RESERVED19:
  746. case PERIPH_ID_W_RESERVED20:
  747. case PERIPH_ID_W_RESERVED23:
  748. case PERIPH_ID_W_RESERVED29:
  749. case PERIPH_ID_W_RESERVED30:
  750. case PERIPH_ID_W_RESERVED31:
  751. return PERIPH_ID_NONE;
  752. default:
  753. return clk_id;
  754. }
  755. }
  756. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  757. void clock_early_init(void)
  758. {
  759. struct clk_rst_ctlr *clkrst =
  760. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  761. struct clk_pll_info *pllinfo;
  762. u32 data;
  763. tegra30_set_up_pllp();
  764. /* clear IDDQ before accessing any other PLLC registers */
  765. pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
  766. clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
  767. udelay(2);
  768. /*
  769. * PLLC output frequency set to 600Mhz
  770. * PLLD output frequency set to 925Mhz
  771. */
  772. switch (clock_get_osc_freq()) {
  773. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  774. clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
  775. clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
  776. break;
  777. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  778. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  779. clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
  780. break;
  781. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  782. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  783. clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
  784. break;
  785. case CLOCK_OSC_FREQ_19_2:
  786. default:
  787. /*
  788. * These are not supported. It is too early to print a
  789. * message and the UART likely won't work anyway due to the
  790. * oscillator being wrong.
  791. */
  792. break;
  793. }
  794. /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
  795. writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
  796. /* PLLC_MISC: Set LOCK_ENABLE */
  797. pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
  798. setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
  799. udelay(2);
  800. /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
  801. pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
  802. data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
  803. data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
  804. writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
  805. udelay(2);
  806. }
  807. /*
  808. * clock_early_init_done - Check if clock_early_init() has been called
  809. *
  810. * Check a register that we set up to see if clock_early_init() has already
  811. * been called.
  812. *
  813. * @return true if clock_early_init() was called, false if not
  814. */
  815. bool clock_early_init_done(void)
  816. {
  817. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  818. u32 val;
  819. val = readl(&clkrst->crc_sclk_brst_pol);
  820. return val == 0x20002222;
  821. }
  822. void arch_timer_init(void)
  823. {
  824. struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
  825. u32 freq, val;
  826. freq = clock_get_rate(CLOCK_ID_CLK_M);
  827. debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
  828. /* ARM CNTFRQ */
  829. asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
  830. /* Only Tegra114+ has the System Counter regs */
  831. debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
  832. writel(freq, &sysctr->cntfid0);
  833. val = readl(&sysctr->cntcr);
  834. val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
  835. writel(val, &sysctr->cntcr);
  836. debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
  837. }
  838. #define PLLE_SS_CNTL 0x68
  839. #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
  840. #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
  841. #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
  842. #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
  843. #define PLLE_SS_CNTL_SSCBYP (1 << 12)
  844. #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
  845. #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
  846. #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
  847. #define PLLE_BASE 0x0e8
  848. #define PLLE_BASE_ENABLE (1 << 30)
  849. #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
  850. #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
  851. #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
  852. #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
  853. #define PLLE_MISC 0x0ec
  854. #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
  855. #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
  856. #define PLLE_MISC_LOCK_ENABLE (1 << 9)
  857. #define PLLE_MISC_PTS (1 << 8)
  858. #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
  859. #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
  860. #define PLLE_AUX 0x48c
  861. #define PLLE_AUX_SEQ_ENABLE (1 << 24)
  862. #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
  863. int tegra_plle_enable(void)
  864. {
  865. unsigned int m = 1, n = 200, cpcon = 13;
  866. u32 value;
  867. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  868. value &= ~PLLE_BASE_LOCK_OVERRIDE;
  869. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  870. value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
  871. value |= PLLE_AUX_ENABLE_SWCTL;
  872. value &= ~PLLE_AUX_SEQ_ENABLE;
  873. writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
  874. udelay(1);
  875. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  876. value |= PLLE_MISC_IDDQ_SWCTL;
  877. value &= ~PLLE_MISC_IDDQ_OVERRIDE;
  878. value |= PLLE_MISC_LOCK_ENABLE;
  879. value |= PLLE_MISC_PTS;
  880. value |= PLLE_MISC_VREG_BG_CTRL(3);
  881. value |= PLLE_MISC_VREG_CTRL(2);
  882. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  883. udelay(5);
  884. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  885. value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
  886. PLLE_SS_CNTL_BYPASS_SS;
  887. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  888. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  889. value &= ~PLLE_BASE_PLDIV_CML(0xf);
  890. value &= ~PLLE_BASE_NDIV(0xff);
  891. value &= ~PLLE_BASE_MDIV(0xff);
  892. value |= PLLE_BASE_PLDIV_CML(cpcon);
  893. value |= PLLE_BASE_NDIV(n);
  894. value |= PLLE_BASE_MDIV(m);
  895. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  896. udelay(1);
  897. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  898. value |= PLLE_BASE_ENABLE;
  899. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  900. /* wait for lock */
  901. udelay(300);
  902. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  903. value &= ~PLLE_SS_CNTL_SSCINVERT;
  904. value &= ~PLLE_SS_CNTL_SSCCENTER;
  905. value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
  906. value &= ~PLLE_SS_CNTL_SSCINC(0xff);
  907. value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
  908. value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
  909. value |= PLLE_SS_CNTL_SSCINC(0x01);
  910. value |= PLLE_SS_CNTL_SSCMAX(0x25);
  911. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  912. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  913. value &= ~PLLE_SS_CNTL_SSCBYP;
  914. value &= ~PLLE_SS_CNTL_BYPASS_SS;
  915. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  916. udelay(1);
  917. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  918. value &= ~PLLE_SS_CNTL_INTERP_RESET;
  919. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  920. udelay(1);
  921. return 0;
  922. }
  923. void clock_sor_enable_edp_clock(void)
  924. {
  925. u32 *reg;
  926. /* uses PLLP, has a non-standard bit layout. */
  927. reg = get_periph_source_reg(PERIPH_ID_SOR0);
  928. setbits_le32(reg, SOR0_CLK_SEL0);
  929. }
  930. u32 clock_set_display_rate(u32 frequency)
  931. {
  932. /**
  933. * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
  934. * = (cf * n) >> p, where 1MHz < cf < 6MHz
  935. * = ((ref / m) * n) >> p
  936. *
  937. * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
  938. * safe vco, then find best (m, n). since m has only 5 bits, we can
  939. * iterate all possible values. Note Tegra 124 supports 11 bits for n,
  940. * but our pll_fields has only 10 bits for n.
  941. *
  942. * Note values undershoot or overshoot target output frequency may not
  943. * work if the values are not in "safe" range by panel specification.
  944. */
  945. u32 ref = clock_get_rate(CLOCK_ID_OSC);
  946. u32 divm, divn, divp, cpcon;
  947. u32 cf, vco, rounded_rate = frequency;
  948. u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
  949. const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
  950. mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
  951. min_cf = 1 * mhz, max_cf = 6 * mhz;
  952. int mux_bits, divider_bits, source;
  953. for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
  954. vco <<= 1;
  955. if (vco < min_vco || vco > max_vco) {
  956. printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
  957. __func__, frequency);
  958. return 0;
  959. }
  960. best_p = divp;
  961. best_diff = vco;
  962. for (divm = 1; divm < max_m && best_diff; divm++) {
  963. cf = ref / divm;
  964. if (cf < min_cf)
  965. break;
  966. if (cf > max_cf)
  967. continue;
  968. divn = vco / cf;
  969. if (divn >= max_n)
  970. continue;
  971. diff = vco - divn * cf;
  972. if (divn + 1 < max_n && diff > cf / 2) {
  973. divn++;
  974. diff = cf - diff;
  975. }
  976. if (diff >= best_diff)
  977. continue;
  978. best_diff = diff;
  979. best_m = divm;
  980. best_n = divn;
  981. }
  982. if (best_n < 50)
  983. cpcon = 2;
  984. else if (best_n < 300)
  985. cpcon = 3;
  986. else if (best_n < 600)
  987. cpcon = 8;
  988. else
  989. cpcon = 12;
  990. if (best_diff) {
  991. printf("%s: Failed to match output frequency %u, best difference is %u\n",
  992. __func__, frequency, best_diff);
  993. rounded_rate = (ref / best_m * best_n) >> best_p;
  994. }
  995. debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
  996. __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
  997. source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
  998. &mux_bits, &divider_bits);
  999. clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
  1000. clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
  1001. return rounded_rate;
  1002. }
  1003. void clock_set_up_plldp(void)
  1004. {
  1005. struct clk_rst_ctlr *clkrst =
  1006. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  1007. u32 value;
  1008. value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
  1009. writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
  1010. clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
  1011. writel(value, &clkrst->crc_plldp_ss_cfg);
  1012. }
  1013. struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
  1014. {
  1015. struct clk_rst_ctlr *clkrst =
  1016. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  1017. if (clkid == CLOCK_ID_DP)
  1018. return &clkrst->plldp;
  1019. return NULL;
  1020. }
  1021. struct periph_clk_init periph_clk_init_table[] = {
  1022. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  1023. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  1024. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  1025. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  1026. { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
  1027. { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
  1028. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  1029. { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
  1030. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  1031. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  1032. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  1033. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  1034. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  1035. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  1036. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  1037. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  1038. { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
  1039. { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
  1040. { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
  1041. { -1, },
  1042. };