cpu.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2014
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/flow.h>
  11. #include <asm/arch/pinmux.h>
  12. #include <asm/arch/tegra.h>
  13. #include <asm/arch-tegra/clk_rst.h>
  14. #include <asm/arch-tegra/pmc.h>
  15. #include <linux/delay.h>
  16. #include "../cpu.h"
  17. /* Tegra114-specific CPU init code */
  18. static void enable_cpu_power_rail(void)
  19. {
  20. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  21. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  22. u32 reg;
  23. debug("%s entry\n", __func__);
  24. /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
  25. pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
  26. pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
  27. /*
  28. * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
  29. * set it for 25ms (102MHz * .025)
  30. */
  31. reg = 0x26E8F0;
  32. writel(reg, &pmc->pmc_cpupwrgood_timer);
  33. /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
  34. clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
  35. setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
  36. /*
  37. * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
  38. * to 408 to satisfy the requirement of having at least 16 CPU clock
  39. * cycles before clamp removal.
  40. */
  41. clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
  42. setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
  43. }
  44. static void enable_cpu_clocks(void)
  45. {
  46. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  47. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
  48. u32 reg;
  49. debug("%s entry\n", __func__);
  50. /* Wait for PLL-X to lock */
  51. do {
  52. reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
  53. } while ((reg & (1 << pllinfo->lock_det)) == 0);
  54. /* Wait until all clocks are stable */
  55. udelay(PLL_STABILIZATION_DELAY);
  56. writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
  57. writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
  58. /* Always enable the main CPU complex clocks */
  59. clock_enable(PERIPH_ID_CPU);
  60. clock_enable(PERIPH_ID_CPULP);
  61. clock_enable(PERIPH_ID_CPUG);
  62. }
  63. static void remove_cpu_resets(void)
  64. {
  65. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  66. u32 reg;
  67. debug("%s entry\n", __func__);
  68. /* Take the slow non-CPU partition out of reset */
  69. reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
  70. writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
  71. /* Take the fast non-CPU partition out of reset */
  72. reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
  73. writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
  74. /* Clear the SW-controlled reset of the slow cluster */
  75. reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
  76. reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
  77. writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
  78. /* Clear the SW-controlled reset of the fast cluster */
  79. reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
  80. reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
  81. reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
  82. reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
  83. reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
  84. writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
  85. }
  86. /**
  87. * Tegra114 requires some special clock initialization, including setting up
  88. * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
  89. */
  90. void t114_init_clocks(void)
  91. {
  92. struct clk_rst_ctlr *clkrst =
  93. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  94. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  95. u32 val;
  96. debug("%s entry\n", __func__);
  97. /* Set active CPU cluster to G */
  98. clrbits_le32(&flow->cluster_control, 1);
  99. writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
  100. debug("Setting up PLLX\n");
  101. init_pllx();
  102. val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
  103. writel(val, &clkrst->crc_clk_sys_rate);
  104. /* Enable clocks to required peripherals. TBD - minimize this list */
  105. debug("Enabling clocks\n");
  106. clock_set_enable(PERIPH_ID_CACHE2, 1);
  107. clock_set_enable(PERIPH_ID_GPIO, 1);
  108. clock_set_enable(PERIPH_ID_TMR, 1);
  109. clock_set_enable(PERIPH_ID_RTC, 1);
  110. clock_set_enable(PERIPH_ID_CPU, 1);
  111. clock_set_enable(PERIPH_ID_EMC, 1);
  112. clock_set_enable(PERIPH_ID_I2C5, 1);
  113. clock_set_enable(PERIPH_ID_FUSE, 1);
  114. clock_set_enable(PERIPH_ID_PMC, 1);
  115. clock_set_enable(PERIPH_ID_APBDMA, 1);
  116. clock_set_enable(PERIPH_ID_MEM, 1);
  117. clock_set_enable(PERIPH_ID_IRAMA, 1);
  118. clock_set_enable(PERIPH_ID_IRAMB, 1);
  119. clock_set_enable(PERIPH_ID_IRAMC, 1);
  120. clock_set_enable(PERIPH_ID_IRAMD, 1);
  121. clock_set_enable(PERIPH_ID_CORESIGHT, 1);
  122. clock_set_enable(PERIPH_ID_MSELECT, 1);
  123. clock_set_enable(PERIPH_ID_EMC1, 1);
  124. clock_set_enable(PERIPH_ID_MC1, 1);
  125. clock_set_enable(PERIPH_ID_DVFS, 1);
  126. /*
  127. * Set MSELECT clock source as PLLP (00), and ask for a clock
  128. * divider that would set the MSELECT clock at 102MHz for a
  129. * PLLP base of 408MHz.
  130. */
  131. clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
  132. CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
  133. /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
  134. clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
  135. /* Give clocks time to stabilize */
  136. udelay(1000);
  137. /* Take required peripherals out of reset */
  138. debug("Taking periphs out of reset\n");
  139. reset_set_enable(PERIPH_ID_CACHE2, 0);
  140. reset_set_enable(PERIPH_ID_GPIO, 0);
  141. reset_set_enable(PERIPH_ID_TMR, 0);
  142. reset_set_enable(PERIPH_ID_COP, 0);
  143. reset_set_enable(PERIPH_ID_EMC, 0);
  144. reset_set_enable(PERIPH_ID_I2C5, 0);
  145. reset_set_enable(PERIPH_ID_FUSE, 0);
  146. reset_set_enable(PERIPH_ID_APBDMA, 0);
  147. reset_set_enable(PERIPH_ID_MEM, 0);
  148. reset_set_enable(PERIPH_ID_CORESIGHT, 0);
  149. reset_set_enable(PERIPH_ID_MSELECT, 0);
  150. reset_set_enable(PERIPH_ID_EMC1, 0);
  151. reset_set_enable(PERIPH_ID_MC1, 0);
  152. reset_set_enable(PERIPH_ID_DVFS, 0);
  153. debug("%s exit\n", __func__);
  154. }
  155. static bool is_partition_powered(u32 partid)
  156. {
  157. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  158. u32 reg;
  159. /* Get power gate status */
  160. reg = readl(&pmc->pmc_pwrgate_status);
  161. return !!(reg & (1 << partid));
  162. }
  163. static bool is_clamp_enabled(u32 partid)
  164. {
  165. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  166. u32 reg;
  167. /* Get clamp status. */
  168. reg = readl(&pmc->pmc_clamp_status);
  169. return !!(reg & (1 << partid));
  170. }
  171. static void power_partition(u32 partid)
  172. {
  173. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  174. debug("%s: part ID = %08X\n", __func__, partid);
  175. /* Is the partition already on? */
  176. if (!is_partition_powered(partid)) {
  177. /* No, toggle the partition power state (OFF -> ON) */
  178. debug("power_partition, toggling state\n");
  179. writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
  180. /* Wait for the power to come up */
  181. while (!is_partition_powered(partid))
  182. ;
  183. /* Wait for the clamp status to be cleared */
  184. while (is_clamp_enabled(partid))
  185. ;
  186. /* Give I/O signals time to stabilize */
  187. udelay(IO_STABILIZATION_DELAY);
  188. }
  189. }
  190. void powerup_cpus(void)
  191. {
  192. /* We boot to the fast cluster */
  193. debug("%s entry: G cluster\n", __func__);
  194. /* Power up the fast cluster rail partition */
  195. power_partition(CRAIL);
  196. /* Power up the fast cluster non-CPU partition */
  197. power_partition(C0NC);
  198. /* Power up the fast cluster CPU0 partition */
  199. power_partition(CE0);
  200. }
  201. void start_cpu(u32 reset_vector)
  202. {
  203. u32 imme, inst;
  204. debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
  205. t114_init_clocks();
  206. /* Enable VDD_CPU */
  207. enable_cpu_power_rail();
  208. /* Get the CPU(s) running */
  209. enable_cpu_clocks();
  210. /* Enable CoreSight */
  211. clock_enable_coresight(1);
  212. /* Take CPU(s) out of reset */
  213. remove_cpu_resets();
  214. /* Set the entry point for CPU execution from reset */
  215. /*
  216. * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
  217. * See nvbug 1193357 for details.
  218. */
  219. /* mov r0, #lsb(reset_vector) */
  220. imme = reset_vector & 0xffff;
  221. inst = imme & 0xfff;
  222. inst |= ((imme >> 12) << 16);
  223. inst |= 0xe3000000;
  224. writel(inst, 0x4003fff0);
  225. /* movt r0, #msb(reset_vector) */
  226. imme = (reset_vector >> 16) & 0xffff;
  227. inst = imme & 0xfff;
  228. inst |= ((imme >> 12) << 16);
  229. inst |= 0xe3400000;
  230. writel(inst, 0x4003fff4);
  231. /* bx r0 */
  232. writel(0xe12fff10, 0x4003fff8);
  233. /* b -12 */
  234. imme = (u32)-20;
  235. inst = (imme >> 2) & 0xffffff;
  236. inst |= 0xea000000;
  237. writel(inst, 0x4003fffc);
  238. /* Write to original location for compatibility */
  239. writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
  240. /* If the CPU(s) don't already have power, power 'em up */
  241. powerup_cpus();
  242. }